📄 adder.rpt
字号:
SW4 | 44 113 | RESERVED
SW5 | 45 112 | RESERVED
SW6 | 46 111 | RESERVED
SW7 | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
S Q Q Q Q Q G Q Q Q R R R V R R R R R V R R R G V C C C G G R V R A B C D E V F G R R R R V R R R R R R
W 0 1 2 3 4 N 5 6 7 E E E C E L L L L C L L L N C L L L N N L C E C E E E E C E E E E E E
8 D S S S C S 0 1 2 3 C 4 5 6 D C K K K D D 7 C S C S S S S C S S S S S S
E E E I E I I 1 1 8 I E I E E E E I E E E E E E
R R R O R N N K 0 H O T N R R R R O R R R R R R
V V V V T T H K z T V V V V V V V V V V
E E E E z H E E E E E E E E E E
D D D D z D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt
adder
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A3 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
A4 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
A5 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
A7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
A8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A13 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
A14 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 10/22( 45%)
A15 8/ 8(100%) 4/ 8( 50%) 7/ 8( 87%) 1/2 0/2 6/22( 27%)
A16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A18 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 0/2 10/22( 45%)
A21 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 11/22( 50%)
A24 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
A26 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A27 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A28 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
A29 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 13/22( 59%)
A30 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 12/22( 54%)
A31 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A32 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A33 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A34 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
A35 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
A36 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B11 4/ 8( 50%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
B14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B28 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 13/22( 59%)
B29 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
B32 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B33 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
B35 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
C1 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
C10 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
C18 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D9 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
D11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
D12 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
D13 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 2/2 1/2 11/22( 50%)
D14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D16 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 4/22( 18%)
D19 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
D27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
D29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
D31 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 13/22( 59%)
D36 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
E1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
E3 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 8/22( 36%)
E6 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 14/22( 63%)
E7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 10/22( 45%)
E11 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
E12 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 13/22( 59%)
E13 3/ 8( 37%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 1/22( 4%)
E14 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 10/22( 45%)
E15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 5/22( 22%)
E17 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 1/2 13/22( 59%)
E18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
E20 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
E21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 13/22( 59%)
E22 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 11/22( 50%)
E23 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 6/22( 27%)
E24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 2/22( 9%)
E29 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
E32 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
E33 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
E34 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 8/22( 36%)
E36 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 12/22( 54%)
F6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
F7 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F8 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F9 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 12/22( 54%)
F11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 11/22( 50%)
F12 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
F13 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
F15 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
F18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 38/141 ( 26%)
Total logic cells used: 510/1728 ( 29%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 1719/6912 ( 24%)
Total input pins required: 20
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 510
Total flipflops required: 157
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 70/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 8 6 7 2 2 1 1 0 0 1 2 8 8 1 8 8 0 0 0 8 0 0 6 8 1 8 8 8 8 8 1 6 5 8 8 170/0
B: 0 0 0 0 0 0 0 0 0 0 4 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 0 0 8 8 0 7 0 44/0
C: 8 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
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