adder.rpt

ＶＨＤＬ 在ＭＡＸＰＬＵＳ环境下运行

Project Information             c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/02/2003 14:01:15

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

adder     EP1K30QC208-3    20     13     8    0         0  %    510      29 %

User Pins:                 20     13     8  



Project Information             c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|ADD:41|:22' stuck at GND
Warning: Flipflop '|ADD:41|:24' stuck at GND
Warning: Flipflop '|ADD:41|:20' stuck at GND
Warning: Flipflop '|ADD:41|:26' stuck at GND
Warning: Flipflop '|ADD:41|:18' stuck at GND
Warning: Flipflop '|SCANDISP:42|:23' stuck at VCC
Info: Reserved unused input pin 'SW5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information             c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

adder@86                          A
adder@87                          B
adder@88                          C
adder@78                          CLK1KHz
adder@80                          CLK8Hz
adder@79                          CLK10KHz
adder@89                          D
adder@90                          E
adder@92                          F
adder@93                          G
adder@170                         KB0
adder@54                          Q0
adder@55                          Q1
adder@56                          Q2
adder@57                          Q3
adder@58                          Q4
adder@60                          Q5
adder@61                          Q6
adder@62                          Q7
adder@172                         RAM_RD
adder@173                         RAM_WR
adder@85                          RESET
adder@68                          RL0
adder@69                          RL1
adder@70                          RL2
adder@71                          RL3
adder@73                          RL4
adder@74                          RL5
adder@75                          RL6
adder@83                          RL7
adder@174                         SS0
adder@175                         SS1
adder@176                         SS2
adder@39                          SW1
adder@40                          SW2
adder@41                          SW3
adder@44                          SW4
adder@45                          SW5
adder@46                          SW6
adder@47                          SW7
adder@53                          SW8


Project Information             c:\acex 1k demo\1k30_208_vhdl\demo20\adder.rpt

** FILE HIERARCHY **



|sync:2|
|sync:2|lpm_add_sub:219|
|sync:2|lpm_add_sub:219|addcore:adder|
|sync:2|lpm_add_sub:219|altshift:result_ext_latency_ffs|
|sync:2|lpm_add_sub:219|altshift:carry_ext_latency_ffs|
|sync:2|lpm_add_sub:219|altshift:oflow_ext_latency_ffs|
|sync:2|lpm_add_sub:271|
|sync:2|lpm_add_sub:271|addcore:adder|
|sync:2|lpm_add_sub:271|altshift:result_ext_latency_ffs|
|sync:2|lpm_add_sub:271|altshift:carry_ext_latency_ffs|
|sync:2|lpm_add_sub:271|altshift:oflow_ext_latency_ffs|
|sync:2|lpm_add_sub:434|
|sync:2|lpm_add_sub:434|addcore:adder|
|sync:2|lpm_add_sub:434|altshift:result_ext_latency_ffs|
|sync:2|lpm_add_sub:434|altshift:carry_ext_latency_ffs|
|sync:2|lpm_add_sub:434|altshift:oflow_ext_latency_ffs|
|disp:15|
|disp:15|lpm_add_sub:665|
|disp:15|lpm_add_sub:665|addcore:adder|
|disp:15|lpm_add_sub:665|altshift:result_ext_latency_ffs|
|disp:15|lpm_add_sub:665|altshift:carry_ext_latency_ffs|
|disp:15|lpm_add_sub:665|altshift:oflow_ext_latency_ffs|
|binbcd:18|
|binbcd:18|lpm_add_sub:2347|
|binbcd:18|lpm_add_sub:2347|addcore:adder|
|binbcd:18|lpm_add_sub:2347|altshift:result_ext_latency_ffs|
|binbcd:18|lpm_add_sub:2347|altshift:carry_ext_latency_ffs|
|binbcd:18|lpm_add_sub:2347|altshift:oflow_ext_latency_ffs|
|binbcd:18|divide:U1|
|binbcd:18|divide:U1|lpm_add_sub:76|
|binbcd:18|divide:U1|lpm_add_sub:76|addcore:adder|
|binbcd:18|divide:U1|lpm_add_sub:76|altshift:result_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:76|altshift:carry_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:76|altshift:oflow_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:95|
|binbcd:18|divide:U1|lpm_add_sub:95|addcore:adder|
|binbcd:18|divide:U1|lpm_add_sub:95|altshift:result_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:95|altshift:carry_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:95|altshift:oflow_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:117|
|binbcd:18|divide:U1|lpm_add_sub:117|addcore:adder|
|binbcd:18|divide:U1|lpm_add_sub:117|altshift:result_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:117|altshift:carry_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:117|altshift:oflow_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:142|
|binbcd:18|divide:U1|lpm_add_sub:142|addcore:adder|
|binbcd:18|divide:U1|lpm_add_sub:142|altshift:result_ext_latency_ffs|
|binbcd:18|divide:U1|lpm_add_sub:142|altshift:carry_ext_latency_ffs|