disp.vhd

ＶＨＤＬ源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity disp is
  port(
	clk,reset:	in std_logic;
	KeyValue:in	std_logic_vector(3 downto 0);
	KeyDis:	inout std_logic_vector(7 downto 0));
  end disp;

  architecture arch of disp is
  BEGIN

	getk:PROCESS(clk,reset)
	VARIABLE i:INTEGER RANGE 0 TO 3;
	BEGIN
	  if(reset = '0') then
		KeyDis <= "11111111";
	  elsif(clk'event and clk='1') then
		CASE i IS
		   WHEN 0 =>
					KeyDis(3 downto 0) <= KeyValue;
					KeyDis(7 downto 4) <= "1111";
		   WHEN 1 =>
					KeyDis(7 downto 4) <= KeyDis(3 downto 0);
					KeyDis(3 downto 0) <= KeyValue;
		   WHEN 2 =>
					KeyDis(3 downto 0) <= KeyValue;
					KeyDis(7 downto 4) <= "1111";
		   WHEN 3 =>
					KeyDis(7 downto 4) <= KeyDis(3 downto 0);
					KeyDis(3 downto 0) <= KeyValue;
		END CASE;
		i := i + 1;
      end if;
	END PROCESS getk;

  END arch;