controler.vhd

来自「ＶＨＤＬ源程序」· VHDL 代码 · 共 97 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity controler is
  port(
	clk,clkR,reset:	in std_logic;
	Key:in 		integer range 0 to 255;
	KeyRAM:		inout std_logic_vector(7 downto 0);
	KeySec:		out integer range 0 to 255;
    Act,nWr,nRd:	out std_logic);
  end controler;

  architecture arch of controler is
  SIGNAL Read,Write,Finish,SecData:std_logic;
  BEGIN

	main:PROCESS(clkR,clk,reset)
	VARIABLE i:INTEGER RANGE 0 TO 4;
	VARIABLE preclk:std_logic;
	BEGIN
	  if(reset = '0') then
		Write <= '0';
		Read <= '0';
	  elsif(clkR'event and clkR='0') then
        if(clk = '1') then
		  if(i<4) then
 	  	    if(SecData = '1') then
		       Write <= '1';
	        else
		       Read <= '1';
		    end if;
			i := i + 1;
		  else
		 	Write <= '0';
 		    Read <= '0';
		  end if;
		else
		  i := 0;
	    end if;
      end if;
	END PROCESS main;

	RW:PROCESS(clk,reset)
	BEGIN
	  if(reset = '0') then
		SecData <= '0';
	  elsif(clk'event and clk = '1') then
		SecData <= NOT(SecData);
	  end if;
	END PROCESS RW;

    daopera:PROCESS(clkR,reset,clk)
    VARIABLE opera:INTEGER RANGE 0 TO 7;
    BEGIN
      if(reset = '0') then
		nWr <= '1';
	    nRd <= '1';
		opera := 0;
		Act <= '0';
--		Finish <= '0';
	  elsif(clkR'event and clkR='1') then
		if(Write = '1') then
		   opera := opera + 1;
		   CASE opera IS 
			  WHEN 1 =>
						nWr <= '0';
			  WHEN 2 =>
						KeyRAM <= CONV_STD_LOGIC_VECTOR(Key,8);
			  WHEN 3 =>
						nWr <= '1';
			  WHEN OTHERS =>
						nWr <= '1';
						opera := 0;
		   END CASE;
	    elsif(Read = '1') then
		   opera := opera + 1;
		   CASE opera IS
			  WHEN 1 =>
						nRd <= '0';
						Act <= '0';
			  WHEN 2 =>
						KeySec <= Key;
			  WHEN 3 =>
		  				Act <= '1';
			  WHEN OTHERS =>
						nRd <= '1';
						opera := 0;
		   END CASE;
		end if;
--	    Finish <= '0';
   	  end if;
	end process daopera;
  END arch;