📄 muler.rpt
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B36 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
C10 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
C11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C13 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C16 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
D4 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
D5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
D6 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
D8 8/ 8(100%) 6/ 8( 75%) 7/ 8( 87%) 1/2 0/2 7/22( 31%)
D9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
D10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
D11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
D12 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
D13 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
D14 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
D17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
E2 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
E15 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
E18 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
F11 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
F12 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 2/22( 9%)
F13 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
F14 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
F18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A37 8/16( 50%) 6/16( 37%) 2/16( 12%) 1/2 2/6 9/88( 10%)
B37 6/16( 37%) 1/16( 6%) 5/16( 31%) 1/2 2/6 7/88( 7%)
D37 8/16( 50%) 5/16( 31%) 3/16( 18%) 1/2 2/6 9/88( 10%)
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 38/141 ( 26%)
Total logic cells used: 513/1728 ( 29%)
Total embedded cells used: 22/96 ( 22%)
Total EABs used: 3/6 ( 50%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 1731/6912 ( 25%)
Total input pins required: 20
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 513
Total flipflops required: 146
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 72/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 7 8 2 0 0 1 8 8 8 8 0 0 0 8 7 0 8 1 0 0 0 0 1 0 0 8 0 8 8 8 8 8 8 0 8 147/8
B: 7 8 7 8 3 2 8 8 8 2 4 7 8 5 7 8 8 8 6 8 6 1 0 0 8 0 7 6 0 0 0 8 8 2 8 8 8 194/6
C: 0 0 0 0 0 0 0 0 0 7 8 0 6 2 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31/0
D: 0 0 0 5 8 7 0 8 8 1 8 8 7 6 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 74/8
E: 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
F: 0 0 8 0 0 0 0 0 0 0 7 8 8 8 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47/0
Total: 15 24 22 21 13 9 8 17 24 18 35 31 29 21 15 24 23 20 22 9 6 1 0 0 9 0 7 14 0 8 8 16 16 10 16 8 16 513/22
Device-Specific Information: e:\temp\1k30_208_vhdl\demo21\muler.rpt
muler
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - -- INPUT G ^ 0 0 0 0 CLK1KHZ
80 - - - -- INPUT G ^ 0 0 0 0 CLK8HZ
79 - - - -- INPUT G ^ 0 0 0 0 CLK10KHZ
54 - - - 35 BIDIR ^ 0 1 0 17 Q0
55 - - - 34 BIDIR ^ 0 1 0 17 Q1
56 - - - 33 BIDIR ^ 0 1 0 17 Q2
57 - - - 32 BIDIR ^ 0 1 0 17 Q3
58 - - - 31 BIDIR ^ 0 1 0 15 Q4
60 - - - 30 BIDIR ^ 0 1 0 15 Q5
61 - - - 29 BIDIR ^ 0 1 0 1 Q6
62 - - - 28 BIDIR ^ 0 1 0 1 Q7
85 - - - 16 INPUT ^ 0 0 0 132 RESET
68 - - - 24 INPUT ^ 0 0 0 3 RL0
69 - - - 23 INPUT ^ 0 0 0 4 RL1
70 - - - 22 INPUT ^ 0 0 0 6 RL2
71 - - - 21 INPUT ^ 0 0 0 3 RL3
73 - - - 20 INPUT ^ 0 0 0 5 RL4
74 - - - 20 INPUT ^ 0 0 0 5 RL5
75 - - - 19 INPUT ^ 0 0 0 5 RL6
83 - - - 17 INPUT ^ 0 0 0 3 RL7
39 - - E -- INPUT ^ 0 0 0 0 SW1
40 - - E -- INPUT ^ 0 0 0 0 SW2
41 - - E -- INPUT ^ 0 0 0 0 SW3
44 - - F -- INPUT ^ 0 0 0 0 SW4
45 - - F -- INPUT ^ 0 0 0 0 SW5
46 - - F -- INPUT ^ 0 0 0 0 SW6
47 - - F -- INPUT ^ 0 0 0 0 SW7
53 - - - 36 INPUT ^ 0 0 0 0 SW8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\temp\1k30_208_vhdl\demo21\muler.rpt
muler
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - - 15 OUTPUT 0 1 0 0 A
87 - - - 14 OUTPUT 0 1 0 0 B
88 - - - 14 OUTPUT 0 1 0 0 C
89 - - - 13 OUTPUT 0 1 0 0 D
90 - - - 12 OUTPUT 0 1 0 0 E
92 - - - 11 OUTPUT 0 1 0 0 F
93 - - - 10 OUTPUT 0 1 0 0 G
170 - - - 11 OUTPUT 0 1 0 0 KB0
54 - - - 35 TRI 0 1 0 17 Q0
55 - - - 34 TRI 0 1 0 17 Q1
56 - - - 33 TRI 0 1 0 17 Q2
57 - - - 32 TRI 0 1 0 17 Q3
58 - - - 31 TRI 0 1 0 15 Q4
60 - - - 30 TRI 0 1 0 15 Q5
61 - - - 29 TRI 0 1 0 1 Q6
62 - - - 28 TRI 0 1 0 1 Q7
172 - - - 12 OUTPUT 0 1 0 0 RAM_RD
173 - - - 13 OUTPUT 0 1 0 0 RAM_WR
174 - - - 14 OUTPUT 0 1 0 0 SS0
175 - - - 14 OUTPUT 0 1 0 0 SS1
176 - - - 15 OUTPUT 0 0 0 0 SS2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
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