multiply.vhd

ＶＨＤＬ源程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;

entity multiply is
  port(
	clk:in std_logic; 
	AA:in std_logic_vector(5 downto 0);
	BB:in std_logic_vector(5 downto 0);
	resu: out std_logic_vector(11 downto 0));
  end multiply;

  architecture arch of multiply is

	COMPONENT lpm_mult
	GENERIC (
		LPM_WIDTHA		: POSITIVE;
		LPM_WIDTHB		: POSITIVE;
		LPM_WIDTHP		: POSITIVE;
		LPM_WIDTHS		: POSITIVE;
		USE_EAB		: STRING;
		LPM_PIPELINE		: POSITIVE;
		MAXIMIZE_SPEED		: POSITIVE
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
			clock	: IN STD_LOGIC ;
			result	: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
	END COMPONENT;


  BEGIN
    U1: lpm_mult
	   GENERIC MAP(
					LPM_WIDTHA=>6,
    			   	LPM_WIDTHB=>6,
  				   	LPM_WIDTHS=>1,
				   	LPM_WIDTHP=>14,
					USE_EAB => "ON",
					LPM_PIPELINE=> 1,
					MAXIMIZE_SPEED => 1
				  )
	      PORT MAP(
				    dataa=>AA,
					datab=>BB,
					clock=>clk,
      				result=>resu 
			   	  );
  END arch;