contro1.vhd

来自「ＶＨＤＬ源程序」· VHDL 代码 · 共 52 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity contro1 is
  port(
	clk,nRd,reset,getk:	in std_logic;
	outp:	out std_logic);
  end contro1;

  architecture arch of contro1 is
  BEGIN

	PROCESS(clk,nRd,reset)
    VARIABLE preRd,prek,start:std_logic;
	VARIABLE timer: INTEGER RANGE 0 TO 500;
	BEGIN
     if(reset = '0') then
       outp <= '0';
		preRd := '1';
		start := '0';
		timer := 0;
     elsif(clk'event and clk = '1') then
		if(nRd = '1') then
		   if(preRd = '0') then
			  start := '1';
--			  outp <= '1';
           end if;
	    end if;
		preRd := nRd;
		if(start = '1') then
		   if(timer < 500) then
			  timer := timer + 1;
		   else
			  timer := 0;
			  start := '0';
			  outp <= '1';
		   end if;
		end if;
		if(getk = '1') then
		   if(prek = '0') then
			  outp <= '0';
           end if;
	    end if;
		prek := getk;		
	 end if;
	END PROCESS;

  END arch;