sync.vhd

来自「ＶＨＤＬ源程序」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity sync is
  port(
	clk,reset:in std_logic;
	keyvalue:in std_logic_vector(3 downto 0);
    GetNum:out std_logic;
	Key:out integer range 0 to 255);
  end sync;

  architecture arch of sync is
  BEGIN
    PROCESS(clk,reset)

	variable TheNo:integer range 0 to 1;
    variable KeyNumber:integer range 0 to 127;
	variable Temp:integer range 0 to 127;

    begin
      if(reset = '0') then
		GetNum <= '0';
	  elsif(clk'event and clk='1') then
         if(TheNo = 0) then
			Temp := CONV_INTEGER(keyvalue) * 2;
 			KeyNumber := Temp * 4;
		    KeyNumber := KeyNumber + Temp;
			GetNum <= '0';
 		 else
			Key <= KeyNumber + CONV_INTEGER(keyvalue);
			GetNum <= '1';
	     end if;
         TheNo := TheNo + 1;
   	  end if;
	end process;
  END arch;