fft.vhd

采用按时间抽选的基4原位算法和坐标旋转数字式计算机（CORDIC）算法实现了一个FFT实时谱分析系统。

--FFT--旋转因子乘法器
----------------------------------------------------------------
LIBRARY lpm;
USE lpm.lpm_components.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY ccmul IS 
  GENERIC (W2   :INTEGER:=17;  --Multiplier bit width
           W1   :INTEGER:=9;   --Bit width c+s sum
           W    :INTEGER:=8);   --Input bit width
  PORT(clk  :std_logic;  --clock for the output register
       x_in,y_in,c_in:  in std_logic_vector(W-1 downto 0);
       cps_in,cms_in :  in std_logic_vector(W1-1 downto 0);
       r_out,i_out   :  out std_logic_vector(W-1 downto 0));
END ccmul;

ARCHITECTURE flex OF ccmul IS

  SIGNAL x,y,c:std_logic_vector(w-1 downto 0);--inputs and outputs
  SIGNAL r,i,cmsy,cpsx,xmyc:std_logic_vector(W2-1 downto 0);
  SIGNAL xmy,cps,cms,sxtx,sxty:std_logic_vector(w1-1 downto 0);

BEGIN  
  x  <=x_in;   --x
  y  <=y_in;   --j*y
  c  <=c_in;   --cos
  cps<=cps_in; --cos+sin
  cms<=cms_in; --cos-sin

PROCESS
BEGIN
  WAIT UNTIL clk='1';
  r_out<=r(w2-2 downto w1-1); --Scaling and FF
  i_out<=i(w2-2 downto w1-1); --foe output
END PROCESS;
-------ccmul with 3mul.and 3 add/sub-------------
sxtx   <=x(x'high)&x;               --Possible growth for
SXTY   <=y(y'high)&y;               --sub_1->sign extension

sub_1:lpm_add_sub                   --sub:x-y;
  GENERIC MAP (LPM_WIDTH=>W1,LPM_DIRECTION=>"SUB",
               LPM_REPRESENTATION=>"SIGNED")
  PORT MAP(dataa=>sxtx,datab=>sxty,result=>xmy);

mul_1:lpm_mult                       --Multiply  (x-y)*c=xmyc
  GENERIC  MAP (LPM_WIDTHA=>W1,LPM_WIDTHB=>W,
                LPM_WIDTHP=>W2,LPM_WIDTHS=>W2,
                LPM_REPRESENTATION=>"SIGNED")
  PORT MAP (dataa=>xmy,datab=>c,result=>xmyc);

mul_2:lpm_mult                       --Multiply  (c-s)*y=cmsy
  GENERIC  MAP (LPM_WIDTHA=>W1,LPM_WIDTHB=>W,
                LPM_WIDTHP=>W2,LPM_WIDTHS=>W2,
                LPM_REPRESENTATION=>"SIGNED")
  PORT  MAP (dataa=>cms,datab=>y,result=>cmsy);

mul_3:lpm_mult                       --Multiply (c+s)*x =cpsx
  GENERIC  MAP (LPM_WIDTHA=>W1,LPM_WIDTHB=>W,
                LPM_WIDTHP=>W2,LPM_WIDTHS=>W2,
                LPM_REPRESENTATION=>"SIGNED")
  PORT  MAP (dataa=>cps,datab=>x,result=>cpsx);

sub_2:lpm_add_sub                    --sub:i<=(c-s)*x-(x-y)*c
  GENERIC  MAP (LPM_WIDTH =>W2,LPM_DIRECTION=>"SUB",
                LPM_REPRESENTATION=>"SIGNED")
  PORT MAP  (dataa=>cpsx, datab=>xmyc, result=>i);

add_1:lpm_add_sub                    --add:r<=(x-y)*c+(c+s)*y
  GENERIC  MAP (LPM_WIDTH =>W2,LPM_DIRECTION=>"add",
                LPM_REPRESENTATION=>"SIGNED")
  PORT MAP  (dataa=>cmsy, datab=>xmyc, result=>r);
END flex;


-----------------------------------------------------------------
--蝶型处理器---------------------------------------------------
-------------------------------------------------------------------
LIBRARY lpm;
USE lpm.lpm_components.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

PACKAGE mul_package IS                   --user defined components
  COMPONENT  ccmul 
    GENERIC (w2:integer:=17; --multiplier bit width 
             w1:integer:=9;  --bit width c+s sum
             w :integer:=8); --input bit width
  PORT
  (clk  :in std_logic;  --clock for output  register
  x_in,y_in,c_in:in std_logic_vector(W-1 downto 0); 
                                                 ---inputs
  cps_in,cms_in  :in std_logic_vector(W1-1 downto 0);
                                                 ---inputs
  r_out,i_out  :out std_logic_vector(W-1 downto 0));
                                                 --results
END COMPONENT;
END mul_package;

LIBRARY work;
USE WORK.MUL_PACKAGE.ALL;


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fft IS
  GENERIC ( W2 :INTEGER :=17; --MULtiplier  bit width
            W1 :integer :=9;  --bit width c+s sum
            W  :integer :=8);  --input bit width
  PORT
  (clk     :std_logic;
   are_in,aim_in,c_in,    --8 bit inputs
   Bre_in,Bim_in     :  in  std_logic_vector( W-1 downto 0);
   cps_in,cms_in     :in std_logic_vector(W1-1 downto 0);
                                     --9 bits  coeffcients
   Dre_out,Dim_out,Ere_out,Eim_out:out std_logic_vector( W-1 downto 0));
END fft;

ARCHITECTURE  flex OF fft IS
  SIGNAL dif_re,dif_im                        --BF out
                      : std_logic_vector(w-1 downto 0);
  SIGNAL Are,Aim ,Bre,Bim  :integer RANGE  -128 to 127;
                                    --inputs as integers
  SIGNAL c    :std_logic_vector(w-1 downto 0);
                                    --input
  SIGNAL cps,cms   :STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
                                     --COEFF IN
  SIGNAL Cre,Cim   : std_logic_vector(w-1 downto 0);
                                           --results
BEGIN
   
  PROCESS   --compute the addition of the bufferfly using
  BEGIN    --integers and store inputs in flip-flops
      WAIT UNTIL clk='1';
      Are <=CONV_INTEGER(Are_in);
      Aim <=CONV_INTEGER(Aim_in);
      bre <=CONV_INTEGER(bre_in);
      bim <=CONV_INTEGER(bim_in);
      
      c     <=c_in;  --load from memory cos
      cps   <=cps_in;  --load from memory cos+sin
      cms   <=cms_in;  --load from memory cos-sin

      Dre_out <=conv_std_logic_vector((Are+Bre)/2,w);
      Dim_out <=conv_std_logic_vector((Aim+Bim)/2,w);
END PROCESS;

--NO FF because butterfly differece "diff" is not an 
PROCESS  (Are ,Bre ,Aim ,Bim)                  --output port
BEGIN
  dif_re <=conv_std_logic_vector(Are/2-Bre/2,8);
  dif_im <=conv_std_logic_vector(Aim/2-Bim/2,8);
END PROCESS;


-- instantiate teh complex twiddle factor multiplier ---
 ccmul_l:ccmul               --multiply  (x+jy)(c+js)
   GENERIC MAP (W2=>W2,W1=>W1,W=>W)
   PORT MAP (clk=>clk,x_in=>dif_re,y_in=>dif_im,
             c_in=>c,  cps_in=>cps,  cms_in=>cms,
             r_out=>Ere_out,i_out=>Eim_out);

END flex;