ram_basic.cr.mti

来自「设计与验证verilog hdl」· MTI 代码 · 共 9 行

C:/prj/Example-4-6/sim/ram_basic_tb.v {1 {vlog -work work C:/prj/Example-4-6/sim/ram_basic_tb.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module ram_basic_tb

Top level modules:
	ram_basic_tb

} {} {}}