bibus.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Mon Jan 02 21:12:00 2006
#
#
#OPTIONS:"|-fixsmult|-nram|-divnmod|-I|C:\\prj\\Example-5-1\\bibus\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v":1102487888
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v":1102487888
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\prj\\Example-5-1\\bibus\\decode.v":1136207518
#CUR:"C:\\prj\\Example-5-1\\bibus\\decode.v":1136207518
#CUR:"C:\\prj\\Example-5-1\\bibus\\bibus.v":1136207458
#CUR:"C:\\prj\\Example-5-1\\bibus\\bibus.v":1136207458
f "C:\eda\synplicity\fpga_81\lib\altera\altera.v"; # file 0
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; # file 1
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; # file 2
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"; # file 3
af .is_verilog 1;
f "C:\prj\Example-5-1\bibus\decode.v"; # file 4
af .is_verilog 1;
f "C:\prj\Example-5-1\bibus\bibus.v"; # file 5
af .is_verilog 1;
@E
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