bibus.xrf

设计与验证verilog hdl

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v, synplify
source_file = 3, c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, c:\prj\example-5-1\bibus\decode.v, synplify
source_file = 6, c:\prj\example-5-1\bibus\bibus.v, synplify
design_name=bibus
instance = port, clk, , bibus, 6, 2:12:2:14
instance = port, rst, , bibus, 6, 2:17:2:19
instance = port, sel, , bibus, 6, 2:22:2:24
instance = port, data_bus[7:0], , bibus, 6, 4:12:4:19
instance = port, addr[7:0], , bibus, 6, 3:12:3:15
instance = comp, addr_in_7_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_6_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_5_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_4_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_3_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_2_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_1_, , bibus, 6, 3:12:3:15
instance = comp, addr_in_0_, , bibus, 6, 3:12:3:15
instance = comp, sel_in, , bibus, 6, 2:22:2:24
instance = comp, rst_in, , bibus, 6, 2:17:2:19
instance = comp, clk_in, , bibus, 6, 2:12:2:14
instance = comp, data_bus_tri_7_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_6_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_5_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_4_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_3_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_2_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_1_, , bibus, 6, 4:12:4:19
instance = comp, data_bus_tri_0_, , bibus, 6, 4:12:4:19
instance = comp, decode_inst, , bibus, 6, 10:7:10:17
design_name=decode
instance = comp, data_bus_out_7__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_6__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_5__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_4__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_3__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_2__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_1__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_0__Z, , decode, 5, 11:0:11:5
instance = comp, data_bus_out_7_0_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_1_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_2_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_3_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_4_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_5_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_6_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out_7_7_, , decode, 5, 15:9:15:12
instance = comp, data_bus_out19_a_cZ, , decode, 5, 15:9:15:12
instance = comp, data_bus_out19_cZ, , decode, 5, 15:9:15:12
instance = comp, un1_data_bus_out20_1_cZ, , decode, 5, 11:0:11:5
instance = comp, data_bus_out19_0_x_cZ, , decode, 5, 15:9:15:12
instance = comp, un1_data_bus_out20_1_a_s_cZ, , decode, 5, 11:0:11:5
instance = comp, un1_data_bus_out20_1_a_x_cZ, , decode, 5, 11:0:11:5