complex_bibus2.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Mon Jan 02 21:43:33 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"
@I::"C:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"C:\prj\Example-5-1\complex_bibus\counter.v"
@I::"C:\prj\Example-5-1\complex_bibus\decode.v"
@I::"C:\prj\Example-5-1\complex_bibus\complex_bibus2.v"
Verilog syntax check successful!
File C:\prj\Example-5-1\complex_bibus\complex_bibus2.v changed - recompiling
Selecting top level module complex_bibus
@N:"C:\prj\Example-5-1\complex_bibus\decode.v":1:7:1:12|Synthesizing module decode

@N:"C:\prj\Example-5-1\complex_bibus\counter.v":2:7:2:13|Synthesizing module counter

@N:"C:\prj\Example-5-1\complex_bibus\complex_bibus2.v":1:7:1:19|Synthesizing module complex_bibus

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jan 02 21:43:33 2006

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Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


Automatic dissolve at startup in view:work.complex_bibus(verilog) of counter_inst(counter)
@N: MT204 |Autoconstrain Mode is ON
RTL optimization done.
Automatic dissolve during optimization of view:work.complex_bibus(verilog) of decode_inst(decode)

Writing Analyst data base C:\prj\Example-5-1\complex_bibus\rev_1\complex_bibus2.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to C:\prj\Example-5-1\complex_bibus\rev_1\complex_bibus2.xrf
Found clock complex_bibus|clk with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jan 02 21:43:34 2006
#


Top view:               complex_bibus
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

##### START OF AREA REPORT #####[
Design view:work.complex_bibus(verilog)
Selecting part EP2C5Q208C6
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

Total combinational functions 31 
Logic element usage by number of inputs
		  4 input functions 	 20
		  3 input functions 	 2
		  <=2 input functions 	 9
Logic elements by mode
		  normal mode            23
		  arithmetic mode        8
Total registers 16 
I/O pins 21 

DSP Blocks:     0  (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 13 blocks (104 nine-bit).
ShiftTap:       0  (0 registers)
Total ESB:      0 bits 

##### END OF AREA REPORT #####]

Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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