complex_bibus.vqm

设计与验证verilog hdl

//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Mon Jan 02 21:43:57 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\eda\synplicity\fpga_81\lib\altera\altera.v "
// file 2 "\c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v "
// file 3 "\c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v "
// file 4 "\c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v "
// file 5 "\c:\prj\example-5-1\complex_bibus\counter.v "
// file 6 "\c:\prj\example-5-1\complex_bibus\decode.v "
// file 7 "\c:\prj\example-5-1\complex_bibus\complex_bibus.v "

// VQM4.1+ 
module decode (
  data_bus_c_7,
  data_bus_c_6,
  data_bus_c_5,
  data_bus_c_4,
  data_bus_c_3,
  data_bus_c_2,
  data_bus_c_1,
  data_bus_c_0,
  addr_c_7,
  addr_c_2,
  addr_c_3,
  addr_c_5,
  addr_c_6,
  addr_c_4,
  addr_c_1,
  addr_c_0,
  data_bus_out_0,
  data_bus_out_1,
  data_bus_out_2,
  data_bus_out_3,
  data_bus_out_4,
  data_bus_out_5,
  data_bus_out_6,
  data_bus_out_7,
  rst_c,
  clk_c
);
input data_bus_c_7 ;
input data_bus_c_6 ;
input data_bus_c_5 ;
input data_bus_c_4 ;
input data_bus_c_3 ;
input data_bus_c_2 ;
input data_bus_c_1 ;
input data_bus_c_0 ;
input addr_c_7 ;
input addr_c_2 ;
input addr_c_3 ;
input addr_c_5 ;
input addr_c_6 ;
input addr_c_4 ;
input addr_c_1 ;
input addr_c_0 ;
output data_bus_out_0 ;
output data_bus_out_1 ;
output data_bus_out_2 ;
output data_bus_out_3 ;
output data_bus_out_4 ;
output data_bus_out_5 ;
output data_bus_out_6 ;
output data_bus_out_7 ;
input rst_c ;
input clk_c ;
wire data_bus_c_7 ;
wire data_bus_c_6 ;
wire data_bus_c_5 ;
wire data_bus_c_4 ;
wire data_bus_c_3 ;
wire data_bus_c_2 ;
wire data_bus_c_1 ;
wire data_bus_c_0 ;
wire addr_c_7 ;
wire addr_c_2 ;
wire addr_c_3 ;
wire addr_c_5 ;
wire addr_c_6 ;
wire addr_c_4 ;
wire addr_c_1 ;
wire addr_c_0 ;
wire data_bus_out_0 ;
wire data_bus_out_1 ;
wire data_bus_out_2 ;
wire data_bus_out_3 ;
wire data_bus_out_4 ;
wire data_bus_out_5 ;
wire data_bus_out_6 ;
wire data_bus_out_7 ;
wire rst_c ;
wire clk_c ;
wire [7:0] data_bus_out_7_Z;
wire un1_data_bus_out20_1 ;
wire data_bus_out19_a ;
wire data_bus_out19 ;
wire data_bus_out19_0_x ;
wire un1_data_bus_out20_1_a_x ;
wire un1_data_bus_out20_1_a_s ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @6:11
  cycloneii_lcell_ff data_bus_out_7__Z (
	.regout(data_bus_out_7),
	.datain(data_bus_out_7_Z[7]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_6__Z (
	.regout(data_bus_out_6),
	.datain(data_bus_out_7_Z[6]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_5__Z (
	.regout(data_bus_out_5),
	.datain(data_bus_out_7_Z[5]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_4__Z (
	.regout(data_bus_out_4),
	.datain(data_bus_out_7_Z[4]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_3__Z (
	.regout(data_bus_out_3),
	.datain(data_bus_out_7_Z[3]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_2__Z (
	.regout(data_bus_out_2),
	.datain(data_bus_out_7_Z[2]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_1__Z (
	.regout(data_bus_out_1),
	.datain(data_bus_out_7_Z[1]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:11
  cycloneii_lcell_ff data_bus_out_0__Z (
	.regout(data_bus_out_0),
	.datain(data_bus_out_7_Z[0]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @6:15
  cycloneii_lcell_comb data_bus_out_7_0_ (
	.combout(data_bus_out_7_Z[0]),
	.dataa(addr_c_0),
	.datab(addr_c_1),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_0)
);
defparam data_bus_out_7_0_.lut_mask="f101";
defparam data_bus_out_7_0_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_1_ (
	.combout(data_bus_out_7_Z[1]),
	.dataa(addr_c_0),
	.datab(addr_c_1),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_1)
);
defparam data_bus_out_7_1_.lut_mask="f101";
defparam data_bus_out_7_1_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_2_ (
	.combout(data_bus_out_7_Z[2]),
	.dataa(addr_c_0),
	.datab(addr_c_1),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_2)
);
defparam data_bus_out_7_2_.lut_mask="f101";
defparam data_bus_out_7_2_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_3_ (
	.combout(data_bus_out_7_Z[3]),
	.dataa(addr_c_0),
	.datab(addr_c_1),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_3)
);
defparam data_bus_out_7_3_.lut_mask="f101";
defparam data_bus_out_7_3_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_4_ (
	.combout(data_bus_out_7_Z[4]),
	.dataa(addr_c_4),
	.datab(addr_c_6),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_4)
);
defparam data_bus_out_7_4_.lut_mask="f101";
defparam data_bus_out_7_4_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_5_ (
	.combout(data_bus_out_7_Z[5]),
	.dataa(addr_c_4),
	.datab(addr_c_6),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_5)
);
defparam data_bus_out_7_5_.lut_mask="f101";
defparam data_bus_out_7_5_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_6_ (
	.combout(data_bus_out_7_Z[6]),
	.dataa(addr_c_4),
	.datab(addr_c_6),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_6)
);
defparam data_bus_out_7_6_.lut_mask="f101";
defparam data_bus_out_7_6_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out_7_7_ (
	.combout(data_bus_out_7_Z[7]),
	.dataa(addr_c_4),
	.datab(addr_c_6),
	.datac(un1_data_bus_out20_1),
	.datad(data_bus_c_7)
);
defparam data_bus_out_7_7_.lut_mask="f101";
defparam data_bus_out_7_7_.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out19_a_cZ (
	.combout(data_bus_out19_a),
	.dataa(addr_c_5),
	.datab(addr_c_4),
	.datac(addr_c_3),
	.datad(addr_c_2)
);
defparam data_bus_out19_a_cZ.lut_mask="1000";
defparam data_bus_out19_a_cZ.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out19_cZ (
	.combout(data_bus_out19),
	.dataa(addr_c_0),
	.datab(addr_c_1),
	.datac(data_bus_out19_0_x),
	.datad(data_bus_out19_a)
);
defparam data_bus_out19_cZ.lut_mask="8000";
defparam data_bus_out19_cZ.sum_lutc_input="datac";
// @6:11
  cycloneii_lcell_comb un1_data_bus_out20_1_cZ (
	.combout(un1_data_bus_out20_1),
	.dataa(addr_c_4),
	.datab(addr_c_6),
	.datac(un1_data_bus_out20_1_a_x),
	.datad(data_bus_out19)
);
defparam un1_data_bus_out20_1_cZ.lut_mask="00f6";
defparam un1_data_bus_out20_1_cZ.sum_lutc_input="datac";
// @6:15
  cycloneii_lcell_comb data_bus_out19_0_x_cZ (
	.combout(data_bus_out19_0_x),
	.dataa(VCC),
	.datab(VCC),
	.datac(addr_c_7),
	.datad(addr_c_6)
);
defparam data_bus_out19_0_x_cZ.lut_mask="000f";
defparam data_bus_out19_0_x_cZ.sum_lutc_input="datac";
// @6:11
  cycloneii_lcell_comb un1_data_bus_out20_1_a_s_cZ (
	.combout(un1_data_bus_out20_1_a_s),
	.dataa(addr_c_3),
	.datab(addr_c_2),
	.datac(addr_c_1),
	.datad(addr_c_0)
);
defparam un1_data_bus_out20_1_a_s_cZ.lut_mask="fffe";
defparam un1_data_bus_out20_1_a_s_cZ.sum_lutc_input="datac";
// @6:11
  cycloneii_lcell_comb un1_data_bus_out20_1_a_x_cZ (
	.combout(un1_data_bus_out20_1_a_x),
	.dataa(VCC),
	.datab(addr_c_7),
	.datac(addr_c_5),
	.datad(un1_data_bus_out20_1_a_s)
);
defparam un1_data_bus_out20_1_a_x_cZ.lut_mask="ff3f";
defparam un1_data_bus_out20_1_a_x_cZ.sum_lutc_input="datac";
endmodule /* decode */

// VQM4.1+ 
module counter (
  data_bus_c_7,
  data_bus_c_6,
  data_bus_c_5,
  data_bus_c_4,
  data_bus_c_3,
  data_bus_c_2,
  data_bus_c_1,
  data_bus_c_0,
  cnt_out_0,
  cnt_out_1,
  cnt_out_2,
  cnt_out_3,
  cnt_out_4,
  cnt_out_5,
  cnt_out_6,
  cnt_out_7,
  I_32_x_i,
  rst_c,
  clk_c
);
input data_bus_c_7 ;
input data_bus_c_6 ;
input data_bus_c_5 ;
input data_bus_c_4 ;
input data_bus_c_3 ;
input data_bus_c_2 ;
input data_bus_c_1 ;
input data_bus_c_0 ;
output cnt_out_0 ;
output cnt_out_1 ;
output cnt_out_2 ;
output cnt_out_3 ;
output cnt_out_4 ;
output cnt_out_5 ;
output cnt_out_6 ;
output cnt_out_7 ;
input I_32_x_i ;
input rst_c ;
input clk_c ;
wire data_bus_c_7 ;
wire data_bus_c_6 ;
wire data_bus_c_5 ;
wire data_bus_c_4 ;
wire data_bus_c_3 ;
wire data_bus_c_2 ;
wire data_bus_c_1 ;
wire data_bus_c_0 ;
wire cnt_out_0 ;
wire cnt_out_1 ;
wire cnt_out_2 ;
wire cnt_out_3 ;
wire cnt_out_4 ;
wire cnt_out_5 ;
wire cnt_out_6 ;
wire cnt_out_7 ;
wire I_32_x_i ;
wire rst_c ;
wire clk_c ;
wire [7:1] un3_cnt_out_combout;
wire [5:0] un3_cnt_out_cout;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @5:16
  cycloneii_lcell_ff cnt_out_7__Z (
	.regout(cnt_out_7),
	.datain(un3_cnt_out_combout[7]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_6__Z (
	.regout(cnt_out_6),
	.datain(un3_cnt_out_combout[6]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_5__Z (
	.regout(cnt_out_5),
	.datain(un3_cnt_out_combout[5]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_4__Z (
	.regout(cnt_out_4),
	.datain(un3_cnt_out_combout[4]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_3__Z (
	.regout(cnt_out_3),
	.datain(un3_cnt_out_combout[3]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_2__Z (
	.regout(cnt_out_2),
	.datain(un3_cnt_out_combout[2]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_1__Z (
	.regout(cnt_out_1),
	.datain(un3_cnt_out_combout[1]),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:16
  cycloneii_lcell_ff cnt_out_0__Z (
	.regout(cnt_out_0),
	.datain(I_32_x_i),
	.clk(clk_c),
	.aclr(rst_c)
);
// @5:20
  cycloneii_lcell_comb un3_cnt_out_0_ (
	.cout(un3_cnt_out_cout[0]),
	.dataa(data_bus_c_0),
	.datab(data_bus_c_1),
	.datac(VCC),
	.datad(VCC)
);
defparam un3_cnt_out_0_.lut_mask="0088";
defparam un3_cnt_out_0_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_1_ (
	.combout(un3_cnt_out_combout[1]),
	.cout(un3_cnt_out_cout[1]),
	.dataa(data_bus_c_0),
	.datab(data_bus_c_1),
	.datac(VCC),
	.datad(VCC)
);
defparam un3_cnt_out_1_.lut_mask="6688";
defparam un3_cnt_out_1_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_2_ (
	.combout(un3_cnt_out_combout[2]),
	.cout(un3_cnt_out_cout[2]),
	.dataa(data_bus_c_2),
	.datab(data_bus_c_3),
	.datac(VCC),
	.datad(VCC),
	.cin(un3_cnt_out_cout[0])
);
defparam un3_cnt_out_2_.lut_mask="5a80";
defparam un3_cnt_out_2_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_3_ (
	.combout(un3_cnt_out_combout[3]),
	.cout(un3_cnt_out_cout[3]),
	.dataa(data_bus_c_2),
	.datab(data_bus_c_3),
	.datac(VCC),
	.datad(VCC),
	.cin(un3_cnt_out_cout[1])
);
defparam un3_cnt_out_3_.lut_mask="6c80";
defparam un3_cnt_out_3_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_4_ (
	.combout(un3_cnt_out_combout[4]),
	.cout(un3_cnt_out_cout[4]),
	.dataa(data_bus_c_4),
	.datab(data_bus_c_5),
	.datac(VCC),
	.datad(VCC),
	.cin(un3_cnt_out_cout[2])
);
defparam un3_cnt_out_4_.lut_mask="5a80";
defparam un3_cnt_out_4_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_5_ (
	.combout(un3_cnt_out_combout[5]),
	.cout(un3_cnt_out_cout[5]),
	.dataa(data_bus_c_4),
	.datab(data_bus_c_5),
	.datac(VCC),
	.datad(VCC),
	.cin(un3_cnt_out_cout[3])
);
defparam un3_cnt_out_5_.lut_mask="6c80";
defparam un3_cnt_out_5_.sum_lutc_input="cin";
// @5:20
  cycloneii_lcell_comb un3_cnt_out_6_ (
	.combout(un3_cnt_out_combout[6]),