sim_clock_edge.mpf

设计与验证verilog hdl

;
; Copyright Model Technology, a Mentor Graphics Corporation company 2004,
; All rights reserved.
;

[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
ieeepure = $MODEL_TECH/../ieeepure
vital2.2b = $MODEL_TECH/../vital2.2b
;
; Lattice Primitive Libraries
;

; VHDL Section
;
generics = $MODEL_TECH/../lattice/vhdl/mach_gen
gen_aux = $MODEL_TECH/../lattice/vhdl/gen_aux
j2svlib = $MODEL_TECH/../lattice/vhdl/j2svlib
vanmacro = $MODEL_TECH/../lattice/vhdl/vhd_mac
lat_vhd = $MODEL_TECH/../lattice/vhdl/lat_vhd
lat_vitl = $MODEL_TECH/../lattice/vhdl/lat_vitl
lattice = $MODEL_TECH/../lattice/vhdl/lat_vhd
lc4k = $MODEL_TECH/../lattice/vhdl/mach
lc5kve = $MODEL_TECH/../lattice/vhdl/mach
lc5kvg = $MODEL_TECH/../lattice/vhdl/lc5kvg
lc5kb = $MODEL_TECH/../lattice/vhdl/mach
mach = $MODEL_TECH/../lattice/vhdl/mach
gdx2 = $MODEL_TECH/../lattice/vhdl/gdx2
lc5kmx = $MODEL_TECH/../lattice/vhdl/lc5kmx
lava1 = $MODEL_TECH/../lattice/vhdl/lava1
xpga = $MODEL_TECH/../lattice/vhdl/lava1
neoprims = $MODEL_TECH/../lattice/vhdl/orca/neoprims/mti/work
orca2 = $MODEL_TECH/../lattice/vhdl/orca/orca2/mti/work
orca3 = $MODEL_TECH/../lattice/vhdl/orca/orca3/mti/work
orca4 = $MODEL_TECH/../lattice/vhdl/orca/orca4/mti/work

sc = $MODEL_TECH/../lattice/vhdl/orca/orca5/mti/work
xp = $MODEL_TECH/../lattice/vhdl/orca/magma/mti/work
ec = $MODEL_TECH/../lattice/vhdl/orca/ec/mti/work
ecp = $MODEL_TECH/../lattice/vhdl/orca/ecp/mti/work


; Verilog Section
;
mgen_vlog = $MODEL_TECH/../lattice/verilog/mgen_vlog
j2svlib = $MODEL_TECH/../lattice/verilog/mgen_vlog
vlog_macro = $MODEL_TECH/../lattice/verilog/vlog_mac
lsc_vlg = $MODEL_TECH/../lattice/verilog/lsc
lscsub_vlg = $MODEL_TECH/../lattice/verilog/lscsub
lc4k_vlg = $MODEL_TECH/../lattice/verilog/mach
lc5kve_vlg = $MODEL_TECH/../lattice/verilog/mach
lc5kb_vlg = $MODEL_TECH/../lattice/verilog/mach
;lc5kva_vlg = $MODEL_TECH/../lattice/verilog/mach
lc5kvg_vlg = $MODEL_TECH/../lattice/verilog/lc5kvg
mach_vlg = $MODEL_TECH/../lattice/verilog/mach
gdx2_vlg = $MODEL_TECH/../lattice/verilog/gdx2
lc5kmx_vlg = $MODEL_TECH/../lattice/verilog/lc5kmx
lava1_vlg = $MODEL_TECH/../lattice/verilog/lava1
xpga_vlg = $MODEL_TECH/../lattice/verilog/lava1
neoprims_vlg = $MODEL_TECH/../lattice/verilog/orca/neoprims
orca2_vlg = $MODEL_TECH/../lattice/verilog/orca/orca2
orca2a_vlg = $MODEL_TECH/../lattice/verilog/orca/orca2a
orca3_vlg = $MODEL_TECH/../lattice/verilog/orca/orca3
orca4_vlg = $MODEL_TECH/../lattice/verilog/orca/orca4
orli10g_work = $MODEL_TECH/../lattice/verilog/orca/orli10g_work
ort8850_work = $MODEL_TECH/../lattice/verilog/orca/ort8850_work
orso82g5_work = $MODEL_TECH/../lattice/verilog/orca/orso82g5_work
orspi4_work = $MODEL_TECH/../lattice/verilog/orca/orspi4_work
ort82g5_work = $MODEL_TECH/../lattice/verilog/orca/ort82g5_work
sysbus_work = $MODEL_TECH/../lattice/verilog/orca/sysbus_work

sc_vlg = $MODEL_TECH/../lattice/verilog/orca/orca5
xp_vlg = $MODEL_TECH/../lattice/verilog/orca/magma
ecp_vlg = $MODEL_TECH/../lattice/verilog/orca/ecp
ec_vlg = $MODEL_TECH/../lattice/verilog/orca/ec


ip_lib = ../../lib/modelsim/IP_WORK
work = work
[vcom]
; VHDL93 variable selects language version as the default. 
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explict enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messges. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1

; Treat as errors:
;   case statement static warnings
;   warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:
;    -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1

; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1

[vlog]

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Turn on incremental compilation of modules. Default is off.
; Incremental = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
vlog95compat = 0

[sccom]
; Disable SystemC name binding during compilation. Default is off.
; NoNameBind = 1

; Enable use of SCV include files and library.  Default is off.
; UseScv = 1

; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g

; Use custom C++ compiler located at this path rather than ModelSim default.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++

; Enable verbose messages from sccom.  Default is off.
; SccomVerbose = 1

; sccom logfile.  Default is no logfile.
; SccomLogfile = sccom.log


[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 1ns

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = ns

; Default run length
RunLength = 100 ns

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Directives to license manager can be set either as single value or as
; space separated multi-values: