transcript

设计与验证verilog hdl

# Reading C:/Modeltech_5.8b/tcl/vsim/pref.tcl 
# //  ModelSim SE 5.8b Jan 01 2004 
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
#  OpenFile "C:/prj/Example-4-2/sim/vsim.wlf" 
project open C:/prj/Example-4-2/sim/sim_clock_edge.mpf
# Loading project sim_clock_edge
# Compile of clock_edge_tb.v was successful.
# Compile of clock_edge.v failed with 1 errors.
# 2 compiles, 1 failed with 1 error. 
# Compile of clock_edge_tb.v was successful.
# Compile of clock_edge.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.clock_edge_tb
# vsim work.clock_edge_tb 
# Loading work.clock_edge_tb
# Loading work.clock_edge
view wave
# .wave
view signals
# .signals
view structure
# .structure
write format wave -window .wave C:/prj/Example-4-2/sim/wave.do
run -all
# Break at C:/prj/Example-4-2/sim/clock_edge_tb.v line 15
quit -sim
# reading C:\Modeltech_5.8b\win32/modelsim.ini
# Loading project clk_3div