un_shannon.xrf

设计与验证verilog hdl

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cyclone.v, synplify
source_file = 3, c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, c:\prj\chapter5\example-5-8\source\un_shannon.v, synplify
design_name=un_shannon
instance = port, in0[7:0], , un_shannon, 5, 2:14:2:16
instance = port, in1[7:0], , un_shannon, 5, 2:19:2:21
instance = port, in2[7:0], , un_shannon, 5, 2:24:2:26
instance = port, late, , un_shannon, 5, 3:6:3:9
instance = port, en, , un_shannon, 5, 3:12:3:13
instance = port, out, , un_shannon, 5, 4:7:4:9
instance = comp, out_cZ, , un_shannon, 5, 5:19:5:54
instance = comp, un6_out_a_0_add7_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add6_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add5_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add4_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add3_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add2_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add1_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, un6_out_a_0_add0_cZ, , un_shannon, 5, 5:19:5:48
instance = comp, en_in, , un_shannon, 5, 3:12:3:13
instance = comp, late_in, , un_shannon, 5, 3:6:3:9
instance = comp, in2_in_7_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_6_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_5_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_4_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_3_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_2_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_1_, , un_shannon, 5, 2:24:2:26
instance = comp, in2_in_0_, , un_shannon, 5, 2:24:2:26
instance = comp, in1_in_7_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_6_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_5_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_4_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_3_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_2_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_1_, , un_shannon, 5, 2:19:2:21
instance = comp, in1_in_0_, , un_shannon, 5, 2:19:2:21
instance = comp, in0_in_7_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_6_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_5_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_4_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_3_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_2_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_1_, , un_shannon, 5, 2:14:2:16
instance = comp, in0_in_0_, , un_shannon, 5, 2:14:2:16
instance = comp, out_out, , un_shannon, 5, 4:7:4:9