un_shannon.srd

设计与验证verilog hdl

f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cyclone.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #file 3
f "c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"; #file 4
f "c:\prj\chapter5\example-5-8\source\un_shannon.v"; #file 5
VNAME 'work.un_shannon.verilog'; # view id 0
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