un_shannon.sxr

设计与验证verilog hdl

BeginView un_shannon NoName
Inst: un6_out_NE_1_a_x   un6_out_NE_1_a_x_cZ stratix_lcell 
Inst: un6_out_NE_2_a_x   un6_out_NE_2_a_x_cZ stratix_lcell 
Inst: un6_out_NE_3_a_x   un6_out_NE_3_a_x_cZ stratix_lcell 
Inst: out   out_cZ stratix_lcell 
Inst: un6_out_NE_6   un6_out_NE_6_cZ stratix_lcell 
Inst: un6_out_NE_6_a   un6_out_NE_6_a_cZ stratix_lcell 
Inst: un6_out_NE_3   un6_out_NE_3_cZ stratix_lcell 
Inst: un6_out_NE_2   un6_out_NE_2_cZ stratix_lcell 
Inst: un6_out_NE_1   un6_out_NE_1_cZ stratix_lcell 
Inst: un6_out_a_0_add7   un6_out_a_0_add7_cZ stratix_lcell 
Inst: un6_out_a_0_add6   un6_out_a_0_add6_cZ stratix_lcell 
Inst: un6_out_a_0_add5   un6_out_a_0_add5_cZ stratix_lcell 
Inst: un6_out_a_0_add4   un6_out_a_0_add4_cZ stratix_lcell 
Inst: un6_out_a_0_add3   un6_out_a_0_add3_cZ stratix_lcell 
Inst: un6_out_a_0_add2   un6_out_a_0_add2_cZ stratix_lcell 
Inst: un6_out_a_0_add1   un6_out_a_0_add1_cZ stratix_lcell 
Inst: un6_out_a_0_add0   un6_out_a_0_add0_cZ stratix_lcell 
Inst: in2_in[7]   in2_in_7_ stratix_io 
Inst: in2_in[6]   in2_in_6_ stratix_io 
Inst: in2_in[5]   in2_in_5_ stratix_io 
Inst: in2_in[4]   in2_in_4_ stratix_io 
Inst: in2_in[3]   in2_in_3_ stratix_io 
Inst: in2_in[2]   in2_in_2_ stratix_io 
Inst: in2_in[1]   in2_in_1_ stratix_io 
Inst: in2_in[0]   in2_in_0_ stratix_io 
Inst: in1_in[7]   in1_in_7_ stratix_io 
Inst: in1_in[6]   in1_in_6_ stratix_io 
Inst: in1_in[5]   in1_in_5_ stratix_io 
Inst: in1_in[4]   in1_in_4_ stratix_io 
Inst: in1_in[3]   in1_in_3_ stratix_io 
Inst: in1_in[2]   in1_in_2_ stratix_io 
Inst: in1_in[1]   in1_in_1_ stratix_io 
Inst: in1_in[0]   in1_in_0_ stratix_io 
Inst: in0_in[7]   in0_in_7_ stratix_io 
Inst: in0_in[6]   in0_in_6_ stratix_io 
Inst: in0_in[5]   in0_in_5_ stratix_io 
Inst: in0_in[4]   in0_in_4_ stratix_io 
Inst: in0_in[3]   in0_in_3_ stratix_io 
Inst: in0_in[2]   in0_in_2_ stratix_io 
Inst: in0_in[1]   in0_in_1_ stratix_io 
Inst: in0_in[0]   in0_in_0_ stratix_io 
EndView un_shannon NoName