latch.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Mon Jan 02 22:48:39 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"C:\prj\Example-5-2\latch.v"
Verilog syntax check successful!
File C:\prj\Example-5-2\latch.v changed - recompiling
Selecting top level module latch
@N:"C:\prj\Example-5-2\latch.v":1:7:1:11|Synthesizing module latch

@W: CL118 :"C:\prj\Example-5-2\latch.v":11:4:11:5|Latch generated from always block for signal data_out, probably caused by a missing assignment in an if or case stmt
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jan 02 22:48:40 2006

###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading Xilinx I/O pad type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/gttype.txt> 


@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
RTL optimization done.

Clock Buffers:
  Inserting Clock buffer for port cond_1,	TNM=cond_1

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.latch(verilog):
No nets needed buffering.

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base C:\prj\Example-5-2\rev_2\latch.srm
Writing EDIF Netlist and constraint files
@W:"c:\prj\example-5-2\latch.v":3:6:3:11|Primary input cond_1 may be a clock input which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jan 02 22:48:41 2006
#


Top view:               latch
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for latch 

Mapping to part: xc3s100evq100-4
Cell usage:
LD              1 use

I/O primitives: 2
IBUF           1 use
OBUF           1 use

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Global Clock Buffers: 1 of 24 (4%)


Mapping Summary:
Total  LUTs: 0 (0%)

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
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