generic.srd

设计与验证verilog hdl

f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\example-4-10\case\case1.v"; #file 2
VNAME 'work.case1.verilog'; # view id 0
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