latch_mult_if.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Wed Jan 18 18:10:03 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\Example-4-10\if_mult\Latch_if_mult\latch_mult_if.v"
Verilog syntax check successful!
File C:\prj\Example-4-10\if_mult\Latch_if_mult\latch_mult_if.v changed - recompiling
Selecting top level module mult_if
@N:"C:\prj\Example-4-10\if_mult\Latch_if_mult\latch_mult_if.v":1:7:1:13|Synthesizing module mult_if

@W: CL118 :"C:\prj\Example-4-10\if_mult\Latch_if_mult\latch_mult_if.v":11:6:11:7|Latch generated from always block for signal z, probably caused by a missing assignment in an if or case stmt
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 18 18:10:03 2006

###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
---------------------------------------
Resource Usage Report
Part: lfec1e-3

Register bits: 0 of 1536 (0%)
Latch bits:      1
I/O cells:       9

Details:
FD1S1AY:        1
IB:             8
OB:             1
ORCALUT4:       4
PFUMX:          1
VHI:            1
VLO:            1
@W:|Net z_1_sqmuxa_2_i appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 18 18:10:05 2006
#


Top view:               mult_if
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]