mult_if.msg

来自「设计与验证verilog hdl」· MSG 代码 · 共 8 行

@TM:1137139359
@N:  :"":0:0:0:-1|Only System clock will be Autoconstrained
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1137139357
@N:  :"c:\prj\example-4-10\if_mult\mult_if.v":1:7:1:13|Synthesizing module mult_if