before_optimized.prj

设计与验证verilog hdl

#-- Synplicity, Inc.
#-- Version 7.5.1     
#-- Project file D:\prj_D\example-s1-1\FHT_example\before_optimized\before_optimized.prj
#-- Written on Tue Jan 25 20:54:33 2005


#add_file options
add_file -verilog "fht_unit1.v"
add_file -verilog "fht_unit2.v"
add_file -verilog "fht_unit3.v"
add_file -verilog "fht_unit4.v"
add_file -verilog "fhtpart.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology CYCLONE
set_option -part EP1C3
set_option -package TC100
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0
set_option -use_fsm_explorer 0

#map options
set_option -frequency 1.000
set_option -fanout_limit 500
set_option -domap 1
set_option -disable_io_insertion 1
set_option -pipe 0
set_option -update_models_cp 0
set_option -retiming 0
set_option -fixgatedclocks 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/fhtpart.vqm"

#implementation attributes
set_option -vlog_std v2001
set_option -synthesis_onoff_pragma 0
set_option -auto_constrain_io 0
impl -active "rev_1"