before_optimized.prd

来自「设计与验证verilog hdl」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version 7.5.1     
#-- Project file D:\prj_D\example-s1-1\FHT_example\before_optimized\before_optimized.prd
#-- Written on Tue Jan 25 20:54:33 2005

#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear