after_optimized.prd

设计与验证verilog hdl

#-- Synplicity, Inc.
#-- Version 7.5.1     
#-- Project file D:\prj_D\example-s1-1\FHT_example\after_optimized\after_optimized.prd
#-- Written on Tue Jan 25 20:54:33 2005

#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear {  Part } {  wch_fht|Clk - Estimated Frequency } {  wch_fht|Clk - Estimated Period } { wch_fht Total LUTs} { wch_fht Logic resources } { wch_fht Register bits } { wch_fht I/O cells }