decode_cmb.tlg

来自「设计与验证verilog hdl」· TLG 代码 · 共 16 行

Selecting top level module decode_cmb
@N:"C:\prj\Example-4-3\decode_cmb.v":1:7:1:16|Synthesizing module decode_cmb

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <5> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <4> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <3> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <2> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <1> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb.v":3:18:3:21|Input port bit <0> of addr[7:0] is unused