decode_cmb2.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Tue Jan 10 03:11:16 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\Example-4-3\decode_cmb2.v"
Verilog syntax check successful!
Selecting top level module decode_cmb2
@N:"C:\prj\Example-4-3\decode_cmb2.v":1:7:1:17|Synthesizing module decode_cmb2

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <5> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <4> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <3> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <2> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <1> of addr[7:0] is unused

@W:"C:\prj\Example-4-3\decode_cmb2.v":3:18:3:21|Input port bit <0> of addr[7:0] is unused

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 10 03:11:16 2006

###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
---------------------------------------
Resource Usage Report
Part: lfec1e-3

Register bits: 0 of 1536 (0%)
I/O cells:       7

Details:
IB:             3
OB:             4
ORCALUT4:       4
VHI:            1
VLO:            1


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 10 03:11:17 2006
#


Top view:               decode_cmb2
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]