clk_3div.edf

设计与验证verilog hdl

(edif (rename CLK_3DIV "clk_3div")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 3 8 22 24 44)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 532R"))
     )
   )
  (external ispmach4s
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell AND2 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
         )
       )
    )
    (cell DFFRH (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port CLK (direction INPUT))
           (port R (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I0 (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I0 (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I0 (direction INPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell (rename CLK_3DIV "clk_3div") (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port clk (direction INPUT))
           (port reset (direction INPUT))
           (port clk_out (direction OUTPUT))
         )
         (contents
          (instance clk1 (viewRef prim (cellRef DFFRH (libraryRef ispmach4s)))
          )
          (instance (rename state_0 "state[0]") (viewRef prim (cellRef DFFRH (libraryRef ispmach4s)))
          )
          (instance (rename state_1 "state[1]") (viewRef prim (cellRef DFFRH (libraryRef ispmach4s)))
          )
          (instance (rename clkZ0 "clk") (viewRef prim (cellRef IBUF (libraryRef ispmach4s)))          )
          (instance (rename resetZ0 "reset") (viewRef prim (cellRef IBUF (libraryRef ispmach4s)))          )
          (instance (rename clk_outZ0 "clk_out") (viewRef prim (cellRef OBUF (libraryRef ispmach4s)))          )
          (instance clk_i (viewRef prim (cellRef INV (libraryRef ispmach4s)))          )
          (instance reset_i (viewRef prim (cellRef INV (libraryRef ispmach4s)))          )
          (instance clk_out_0_a2 (viewRef prim (cellRef AND2 (libraryRef ispmach4s)))          )
          (instance (rename state_i_1 "state_i[1]") (viewRef prim (cellRef INV (libraryRef ispmach4s)))          )
          (instance state22_0_a2 (viewRef prim (cellRef AND2 (libraryRef ispmach4s)))          )
          (net (rename stateZ0Z_1 "state[1]") (joined
           (portRef Q (instanceRef state_1))
           (portRef I0 (instanceRef state_i_1))
          ))
          (net (rename stateZ0Z_0 "state[0]") (joined
           (portRef Q (instanceRef state_0))
           (portRef I0 (instanceRef state22_0_a2))
           (portRef I1 (instanceRef clk_out_0_a2))
           (portRef D (instanceRef clk1))
          ))
          (net (rename clkZ0Z1 "clk1") (joined
           (portRef Q (instanceRef clk1))
           (portRef I0 (instanceRef clk_out_0_a2))
          ))
          (net state22 (joined
           (portRef O (instanceRef state22_0_a2))
           (portRef D (instanceRef state_1))
          ))
          (net (rename state_iZ0Z_1 "state_i[1]") (joined
           (portRef O (instanceRef state_i_1))
           (portRef I1 (instanceRef state22_0_a2))
           (portRef D (instanceRef state_0))
          ))
          (net (rename reset_iZ0 "reset_i") (joined
           (portRef O (instanceRef reset_i))
           (portRef R (instanceRef clk1))
           (portRef R (instanceRef state_0))
           (portRef R (instanceRef state_1))
          ))
          (net (rename clk_iZ0 "clk_i") (joined
           (portRef O (instanceRef clk_i))
           (portRef CLK (instanceRef clk1))
          ))
          (net clk_c (joined
           (portRef O (instanceRef clkZ0))
           (portRef I0 (instanceRef clk_i))
           (portRef CLK (instanceRef state_0))
           (portRef CLK (instanceRef state_1))
          ))
          (net clk (joined
           (portRef clk)
           (portRef I0 (instanceRef clkZ0))
          ))
          (net reset_c (joined
           (portRef O (instanceRef resetZ0))
           (portRef I0 (instanceRef reset_i))
          ))
          (net reset (joined
           (portRef reset)
           (portRef I0 (instanceRef resetZ0))
          ))
          (net clk_out_c (joined
           (portRef O (instanceRef clk_out_0_a2))
           (portRef I0 (instanceRef clk_outZ0))
          ))
          (net clk_out (joined
           (portRef O (instanceRef clk_outZ0))
           (portRef clk_out)
          ))
          (net GND (joined
          ))
          (net VCC (joined
          ))
         )
       )
    )
  )
  (design (rename CLK_3DIV "clk_3div") (cellRef CLK_3DIV (libraryRef work)))
)