clk_div_phase.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Wed Jan 11 02:21:18 2006
#
#
#OPTIONS:"|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|C:\\prj\\Example-4-7\\clk_div_phase\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\prj\\Example-4-7\\clk_div_phase\\clk_div_phase.v":1136917275
#CUR:"C:\\prj\\Example-4-7\\clk_div_phase\\clk_div_phase.v":1136917275
f "C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "C:\prj\Example-4-7\clk_div_phase\clk_div_phase.v"; # file 1
af .is_verilog 1;
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