rpt_clk_div_phase.areasrr
来自「设计与验证verilog hdl」· AREASRR 代码 · 共 55 行
AREASRR
55 行
#### START OF AREA REPORT #####[
Part: XC3S50TQ144-4 (Xilinx)
-----------------------------------------------------------------------------
######## Utilization report for Top level view: clk_div_phase ########
=============================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 6 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block clk_div_phase: 6 (31.58 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 5 100 %
MUXCY 0 0.0 %
XORCY 0 0.0 %
MULT18x18/MULT18x18S 0 0.0 %
=================================================================
Total COMBINATIONAL LOGIC in the block clk_div_phase: 5 (26.32 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Number of bits Utilization Notes
-------------------------------------------------------------------------
SYNC RAMS 0 0 0.0 %
ROMS 0 0 0.0 %
=========================================================================
Total MEMORY ELEMENTS in the block clk_div_phase: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 5 100 %
=================================================
Total IO PADS in the block clk_div_phase: 5 (26.32 % Utilization)
##### END OF AREA REPORT #####]
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