mux2.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Jan 10 23:31:44 2006
#
#
#OPTIONS:"|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|C:\\prj\\Example-4-5\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\prj\\Example-4-5\\mux2.v":1136907102
#CUR:"C:\\prj\\Example-4-5\\mux2.v":1136907102
f "C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "C:\prj\Example-4-5\mux2.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@44::4(::IgRFRs	lRkGPHCsD;Fo
RNP3PH#CDsHF4oR;P
NR#3H_sPCHoDFR
4;N3PRFosHhCNlRk"lG
";
@HR@d4:::4ddc:4RRCMC
M;
@HR@c4:::4dcd:4RNNR;



@HR@c4:::4ncn:4RLLR;



@FR@64:::4d6g:4RGlk_0FkRGlk_0Fk;R
b@:@j4::44R:.0CskRk0sCsR0k
C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
@bR@U4:::4gUg:.RGlkRGlk_0FkRGlk_0FkRNLRR;CM

C;