mux.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Tue Jan 10 23:28:53 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"C:\prj\Example-4-5\mux.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module mux
@N:"C:\prj\Example-4-5\mux.v":1:7:1:9|Synthesizing module mux

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 10 23:28:54 2006

###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading Xilinx I/O pad type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/gttype.txt> 


@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
RTL optimization done.
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.mux(verilog):
No nets needed buffering.

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base C:\prj\Example-4-5\rev_1\mux.srm
Writing EDIF Netlist and constraint files


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 10 23:28:56 2006
#


Top view:               mux
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for mux 

Mapping to part: xc3s50tq144-4
Cell usage:
MUXF5           1 use
LUT3            2 uses

I/O primitives: 7
IBUF           6 uses
OBUF           1 use

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Mapping Summary:
Total  LUTs: 2 (0%)

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
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