mux.xrf

设计与验证verilog hdl

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v, synplify
source_file = 3, c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, c:\prj\example-4-5\mux.v, synplify
design_name=mux
instance = port, en[1:0], , mux, 5, 3:13:3:14
instance = port, a, , mux, 5, 4:13:4:13
instance = port, b, , mux, 5, 4:16:4:16
instance = port, c, , mux, 5, 4:19:4:19
instance = port, d, , mux, 5, 4:22:4:22
instance = port, mux_out, , mux, 5, 5:13:5:19
instance = comp, d_in, , mux, 5, 4:22:4:22
instance = comp, c_in, , mux, 5, 4:19:4:19
instance = comp, b_in, , mux, 5, 4:16:4:16
instance = comp, a_in, , mux, 5, 4:13:4:13
instance = comp, en_in_1_, , mux, 5, 3:13:3:14
instance = comp, en_in_0_, , mux, 5, 3:13:3:14
instance = comp, mux_out_out, , mux, 5, 5:13:5:19