mux.edf

设计与验证verilog hdl

(edif mux
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 1 10 23 28 56)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXF5 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell mux (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename en "en[1:0]") 2) (direction INPUT))
           (port a (direction INPUT)
 )
           (port b (direction INPUT)
 )
           (port c (direction INPUT)
 )
           (port d (direction INPUT)
 )
           (port mux_out (direction OUTPUT))
         )
         (contents
          (instance mux_out_3_0 (viewRef PRIM (cellRef MUXF5 (libraryRef VIRTEX)))
           (property mapinfo (string "F5MUX"))
          )
          (instance mux_out_3_0_bm (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "CA"))
          )
          (instance mux_out_3_0_am (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "CA"))
          )
          (instance mux_out_obuf (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance d_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance c_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance b_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance a_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename en_ibuf_1 "en_ibuf[1]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename en_ibuf_0 "en_ibuf[0]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (net (rename en_0 "en[0]") (joined
           (portRef (member en 1))
           (portRef I (instanceRef en_ibuf_0))
          ))
          (net (rename en_1 "en[1]") (joined
           (portRef (member en 0))
           (portRef I (instanceRef en_ibuf_1))
          ))
          (net a (joined
           (portRef a)
           (portRef I (instanceRef a_ibuf))
          ))
          (net b (joined
           (portRef b)
           (portRef I (instanceRef b_ibuf))
          ))
          (net c (joined
           (portRef c)
           (portRef I (instanceRef c_ibuf))
          ))
          (net d (joined
           (portRef d)
           (portRef I (instanceRef d_ibuf))
          ))
          (net mux_out (joined
           (portRef O (instanceRef mux_out_obuf))
           (portRef mux_out)
          ))
          (net (rename mux_out_3_0_amZ0 "mux_out_3_0_am") (joined
           (portRef O (instanceRef mux_out_3_0_am))
           (portRef I0 (instanceRef mux_out_3_0))
          ))
          (net (rename mux_out_3_0_bmZ0 "mux_out_3_0_bm") (joined
           (portRef O (instanceRef mux_out_3_0_bm))
           (portRef I1 (instanceRef mux_out_3_0))
          ))
          (net (rename en_c_0 "en_c[0]") (joined
           (portRef O (instanceRef en_ibuf_0))
           (portRef S (instanceRef mux_out_3_0))
          ))
          (net mux_out_c (joined
           (portRef O (instanceRef mux_out_3_0))
           (portRef I (instanceRef mux_out_obuf))
          ))
          (net b_c (joined
           (portRef O (instanceRef b_ibuf))
           (portRef I0 (instanceRef mux_out_3_0_bm))
          ))
          (net d_c (joined
           (portRef O (instanceRef d_ibuf))
           (portRef I1 (instanceRef mux_out_3_0_bm))
          ))
          (net (rename en_c_1 "en_c[1]") (joined
           (portRef O (instanceRef en_ibuf_1))
           (portRef I2 (instanceRef mux_out_3_0_am))
           (portRef I2 (instanceRef mux_out_3_0_bm))
          ))
          (net a_c (joined
           (portRef O (instanceRef a_ibuf))
           (portRef I0 (instanceRef mux_out_3_0_am))
          ))
          (net c_c (joined
           (portRef O (instanceRef c_ibuf))
           (portRef I1 (instanceRef mux_out_3_0_am))
          ))
         )
       )
    )
  )
  (design mux (cellRef mux (libraryRef work))
	(property PART (string "xc3s50tq144-4") (owner "Xilinx")))
)