📄 srl2pal.srr
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#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Wed Jan 11 04:09:37 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"C:\prj\Example-4-8\srl2pal.v"
Verilog syntax check successful!
Selecting top level module srl2pal
@N:"C:\prj\Example-4-8\srl2pal.v":1:7:1:13|Synthesizing module srl2pal
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 11 04:09:37 2006
###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May 9 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Reading Xilinx I/O pad type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/gttype.txt>
@N: MT204 |Autoconstrain Mode is ON
RTL optimization done.
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Timing driven replication report
No replication required.
Net buffering Report for view:work.srl2pal(verilog):
No nets needed buffering.
@N: FX164 |The option to pack flops in the IOB has not been specified
Writing Analyst data base C:\prj\Example-4-8\rev_1\srl2pal.srm
Writing EDIF Netlist and constraint files
Found clock srl2pal|clk with period 1.45ns
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 11 04:09:39 2006
#
Top view: srl2pal
Requested Frequency: 691.8 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.255
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
srl2pal|clk 691.8 MHz 588.0 MHz 1.446 1.701 -0.255 inferred Autoconstr_clkgroup_0
========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------
srl2pal|clk srl2pal|clk | 1.446 -0.255 | No paths - | No paths - | No paths -
=================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: srl2pal|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
pal_out[0] srl2pal|clk FDC Q pal_out_c[0] 0.720 -0.255
pal_out[1] srl2pal|clk FDC Q pal_out_c[1] 0.720 -0.255
pal_out[2] srl2pal|clk FDC Q pal_out_c[2] 0.720 -0.255
pal_out[3] srl2pal|clk FDC Q pal_out_c[3] 0.720 -0.255
pal_out[4] srl2pal|clk FDC Q pal_out_c[4] 0.720 -0.255
pal_out[5] srl2pal|clk FDC Q pal_out_c[5] 0.720 -0.255
pal_out[6] srl2pal|clk FDC Q pal_out_c[6] 0.720 -0.255
===================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------
pal_out[1] srl2pal|clk FDC D pal_out_c[0] 1.243 -0.255
pal_out[2] srl2pal|clk FDC D pal_out_c[1] 1.243 -0.255
pal_out[3] srl2pal|clk FDC D pal_out_c[2] 1.243 -0.255
pal_out[4] srl2pal|clk FDC D pal_out_c[3] 1.243 -0.255
pal_out[5] srl2pal|clk FDC D pal_out_c[4] 1.243 -0.255
pal_out[6] srl2pal|clk FDC D pal_out_c[5] 1.243 -0.255
pal_out[7] srl2pal|clk FDC D pal_out_c[6] 1.243 -0.255
====================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1.446
- Setup time: 0.203
= Required time: 1.243
- Propagation time: 1.498
= Slack (critical) : -0.255
Number of logic level(s): 0
Starting point: pal_out[0] / Q
Ending point: pal_out[1] / D
The start point is clocked by srl2pal|clk [rising] on pin C
The end point is clocked by srl2pal|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
pal_out[0] FDC Q Out 0.720 0.720 -
pal_out_c[0] Net - - 0.778 - 2
pal_out[1] FDC D In - 1.498 -
=============================================================================
Total path delay (propagation time + setup) of 1.701 is 0.923(54.3%) logic and 0.778(45.7%) route.
Path information for path number 2:
Requested Period: 1.446
- Setup time: 0.203
= Required time: 1.243
- Propagation time: 1.498
= Slack (critical) : -0.255
Number of logic level(s): 0
Starting point: pal_out[1] / Q
Ending point: pal_out[2] / D
The start point is clocked by srl2pal|clk [rising] on pin C
The end point is clocked by srl2pal|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
pal_out[1] FDC Q Out 0.720 0.720 -
pal_out_c[1] Net - - 0.778 - 2
pal_out[2] FDC D In - 1.498 -
=============================================================================
Total path delay (propagation time + setup) of 1.701 is 0.923(54.3%) logic and 0.778(45.7%) route.
Path information for path number 3:
Requested Period: 1.446
- Setup time: 0.203
= Required time: 1.243
- Propagation time: 1.498
= Slack (critical) : -0.255
Number of logic level(s): 0
Starting point: pal_out[2] / Q
Ending point: pal_out[3] / D
The start point is clocked by srl2pal|clk [rising] on pin C
The end point is clocked by srl2pal|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
pal_out[2] FDC Q Out 0.720 0.720 -
pal_out_c[2] Net - - 0.778 - 2
pal_out[3] FDC D In - 1.498 -
=============================================================================
Total path delay (propagation time + setup) of 1.701 is 0.923(54.3%) logic and 0.778(45.7%) route.
Path information for path number 4:
Requested Period: 1.446
- Setup time: 0.203
= Required time: 1.243
- Propagation time: 1.498
= Slack (critical) : -0.255
Number of logic level(s): 0
Starting point: pal_out[3] / Q
Ending point: pal_out[4] / D
The start point is clocked by srl2pal|clk [rising] on pin C
The end point is clocked by srl2pal|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
pal_out[3] FDC Q Out 0.720 0.720 -
pal_out_c[3] Net - - 0.778 - 2
pal_out[4] FDC D In - 1.498 -
=============================================================================
Total path delay (propagation time + setup) of 1.701 is 0.923(54.3%) logic and 0.778(45.7%) route.
Path information for path number 5:
Requested Period: 1.446
- Setup time: 0.203
= Required time: 1.243
- Propagation time: 1.498
= Slack (critical) : -0.255
Number of logic level(s): 0
Starting point: pal_out[4] / Q
Ending point: pal_out[5] / D
The start point is clocked by srl2pal|clk [rising] on pin C
The end point is clocked by srl2pal|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
pal_out[4] FDC Q Out 0.720 0.720 -
pal_out_c[4] Net - - 0.778 - 2
pal_out[5] FDC D In - 1.498 -
=============================================================================
Total path delay (propagation time + setup) of 1.701 is 0.923(54.3%) logic and 0.778(45.7%) route.
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for srl2pal
Mapping to part: xc3s50tq144-4
Cell usage:
FDC 8 uses
I/O primitives: 10
IBUF 2 uses
OBUF 8 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 8 (0%)
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 0 (0%)
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
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