syn_rst.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Wed Jan 11 15:52:38 2006
#
#
#OPTIONS:"|-fixsmult|-I|C:\\prj\\Example-4-9\\syn_rst\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\xp.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\xp.v":1110443426
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\xp.v":1110443426
#CUR:"C:\\prj\\Example-4-9\\syn_rst\\syn_rst.v":1136965953
#CUR:"C:\\prj\\Example-4-9\\syn_rst\\syn_rst.v":1136965953
f "C:\eda\synplicity\fpga_81\lib\lucent\xp.v"; # file 0
af .is_verilog 1;
f "C:\prj\Example-4-9\syn_rst\syn_rst.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@44::4(::R4dI	FsRM#$_0s#RsPCHoDF;P
NR#3HPHCsDRFo4N;
PHR3#C_PsFHDo;R4
RNP3HFsolhNC#R"$sM_#;0"
@HR@d4:::4dd6:4R	ODR	OD;



@HR@c4:::4dcn:4R0s#_#Rs0
_;
@FR@64:::4d6n:4R0OM4:rcjV9RNCD#,DVN#VC,NCD#,0OM4r_449:j;



@FR@64:::.j6d:.R0OM.:rcjO9RM_0.49r.,0OM.r_4.O9,M_0.4:r.j
9;b@R@4::c4cd::R4nHRMPk_M4s_#0R4kM_0s#_#Rs0
_;b@R@j::44::4.sR0k0CRsRkC0Csk;R
b@:@j4::44R:.V#NDCNRVDR#CV#NDCb;
R4@@::4(44.:(c:.RRD0O4M04OdRM404dMRO044_rj4:9sR0k0C,s;kC
@bR@44:Uj:.::4U.NUR8k8RMO4_M404d9rjR4kM_0OM4r4djO9RM404dMRO044_r;j9
@bR@.4:4n:4::.4.NcR8k8RMOd_Mr0..9:jRdkM_0OM.:r.jO9RM_044:r4j09Rs,kC0Csk,k0sCb;
R4@@::.44.n:4c:.RPHMR4kM_0OM.9r.R4kM_0OM.9r.RdkM_0OM.9r.;R
b@:@4g::jgR:6#V8VsMRO04._rj.:9MRO04._rj.:9MRkdM_O0..r:Rj9ORD	k_M4s_#0;H
NR$3#Ms_bFNOMl"CRbOsF_0OM4
";N3HRFosH_8IH06ER;H
NR03sDs_FHNoMl"CRO.M0"b;
R4@@:jg::6g:RV#8VOsRM_044:r4jO9RM_044:r4jk9RMO4_Mr0..k9,MO4_M404d9rjR	OD
RRRR4kM_0s#_N;
H#R3$bM_sMFONRlC"FbsOM_O0;4"
RNH3Ds0_HFsolMNCOR"M"04;;
C