syn_rst.msg

设计与验证verilog hdl

@TM:1136965846
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1136965842
@N:  :"c:\prj\example-4-9\syn_rst\syn_rst.v":1:7:1:13|Synthesizing module syn_rst
@W: CL171 :"c:\prj\example-4-9\syn_rst\syn_rst.v":9:0:9:5|M
@W: CL189 :"c:\prj\example-4-9\syn_rst\syn_rst.v":9:0:9:5|M
@N: CG179 :"c:\prj\example-4-9\syn_rst\syn_rst.v":20:20:20:23|M