reg_counter.ncf

来自「设计与验证verilog hdl」· NCF 代码 · 共 18 行

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
NET "clock" TNM_NET = "clock"; 
TIMESPEC "TS_clock" = PERIOD "clock" 10.000 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# Location Constraints

# End of generated constraints