state_default.prd

设计与验证verilog hdl

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\FSM_abc\state_default\state_default.prd
#-- Written on Fri Dec 16 16:56:06 2005

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear