cnt1.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Wed Mar 08 20:34:48 2006
#
#
#OPTIONS:"|-I|C:\\prj\\Example-4-1\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\prj\\Example-4-1\\source\\cnt1.v":1141637030
#CUR:"C:\\prj\\Example-4-1\\source\\cnt1.v":1141637030
f "C:\prj\Example-4-1\source\cnt1.v"; # file 0
af .is_verilog 1;
@E
@ 
ftell;
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;

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