top.plg

来自「设计与验证verilog hdl」· PLG 代码 · 共 12 行

@P:  Worst Slack : -4.869
@P:  top|CS_ - Estimated Frequency : 0.9 MHz
@P:  top|CS_ - Requested Frequency : 0.9 MHz
@P:  top|CS_ - Estimated Period : 1137.137
@P:  top|CS_ - Requested Period : 1132.268
@P:  top|CS_ - Slack : -4.869
@P:  top|OE_ - Estimated Frequency : 0.5 MHz
@P:  top|OE_ - Requested Frequency : 283.4 MHz
@P:  top|OE_ - Estimated Period : 2098.494
@P:  top|OE_ - Requested Period : 3.528
@P:  top|OE_ - Slack : -0.623