📄 pack_mips.vhd
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-------------------------------------------------------------------------------------- ---- Copyright (c) 2004, Hangouet Samuel ---- , Jan Sebastien ---- , Mouton Louis-Marie ---- , Schneider Olivier all rights reserved ---- ---- This file is part of miniMIPS. ---- ---- miniMIPS is free software; you can redistribute it and/or modify ---- it under the terms of the GNU General Public License as published by ---- the Free Software Foundation; either version 2 of the License, or ---- (at your option) any later version. ---- ---- miniMIPS is distributed in the hope that it will be useful, ---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ---- GNU General Public License for more details. ---- ---- You should have received a copy of the GNU General Public License ---- along with miniMIPS; if not, write to the Free Software ---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ---- ---------------------------------------------------------------------------------------- If you encountered any problem, please contact :---- lmouton@enserg.fr-- oschneid@enserg.fr-- shangoue@enserg.fr------------------------------------------------------------------------------ ---- ---- Processor miniMIPS : Enumerations and components declarations ---- ---- ---- ---- Authors : Hangouet Samuel ---- Jan S閎astien ---- Mouton Louis-Marie ---- Schneider Olivier ---- ---- june 2003 ----------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;package pack_mips is -- Type signal on n bits subtype bus64 is std_logic_vector(63 downto 0); subtype bus33 is std_logic_vector(32 downto 0); subtype bus32 is std_logic_vector(31 downto 0); subtype bus31 is std_logic_vector(30 downto 0); subtype bus26 is std_logic_vector(25 downto 0); subtype bus24 is std_logic_vector(23 downto 0); subtype bus16 is std_logic_vector(15 downto 0); subtype bus8 is std_logic_vector(7 downto 0); subtype bus6 is std_logic_vector(5 downto 0); subtype bus5 is std_logic_vector(4 downto 0); subtype bus4 is std_logic_vector(3 downto 0); subtype bus2 is std_logic_vector(1 downto 0); subtype bus1 is std_logic; -- Address of a register type subtype adr_reg_type is std_logic_vector(5 downto 0); -- Coding of the level of data availability for UR subtype level_type is std_logic_vector(1 downto 0); constant LVL_DI : level_type := "11"; -- Data available from the op2 of DI stage constant LVL_EX : level_type := "10"; -- Data available from the data_ual register of EX stage constant LVL_MEM : level_type := "01"; -- Data available from the data_ecr register of MEM stage constant LVL_REG : level_type := "00"; -- Data available only in the register bank -- Different values of cause exceptions constant IT_NOEXC : bus32 := X"00000000"; constant IT_ITMAT : bus32 := X"00000001"; constant IT_OVERF : bus32 := X"00000002"; constant IT_ERINS : bus32 := X"00000004"; constant IT_BREAK : bus32 := X"00000008"; constant IT_SCALL : bus32 := X"00000010"; -- Operation type of the coprocessor system (only the low 16 bits are valid) constant SYS_NOP : bus32 := X"0000_0000"; constant SYS_MASK : bus32 := X"0000_0001"; constant SYS_UNMASK : bus32 := X"0000_0002"; constant SYS_ITRET : bus32 := X"0000_0004"; -- Type for the alu control subtype alu_ctrl_type is std_logic_vector(27 downto 0); -- Arithmetical operations constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign
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