fast_div.vhd

实现4位加减乘除的alu

-- 快速除法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
 
ENTITY fast_div IS
	GENERIC(N:	integer	:=	4);
    PORT(divdend	:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);	
		 divisor	:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0); 
         Clk		:IN		STD_LOGIC;
		 load		:IN		STD_LOGIC;
         qout		:OUT	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);	
         done		:OUT	STD_LOGIC);
END fast_div;

ARCHITECTURE Behavior OF fast_div IS
BEGIN
	PROCESS(Clk)
	VARIABLE reg	:	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);
	VARIABLE regM	:	STD_LOGIC_VECTOR(N-1 DOWNTO 0);
	VARIABLE Count	:	INTEGER RANGE 0 TO N;
	BEGIN
		IF Clk'EVENT AND Clk='1' THEN
			IF load = '1' THEN		--加载并赋初值
				done <= '0';
				Count	:= N;
				regM	:= divisor;
				reg(2*N-2 downto N) := (OTHERS=>'0');	--正数全赋1
				reg(N-1 DOWNTO 0)		:= divdend;
			ELSIF Count /= 0 THEN				
				reg(2*N-1 DOWNTO 1) := reg(2*N-2 DOWNTO 0);	--左移
				reg(0)				:= '0';	
				IF(reg(2*N-1 DOWNTO N) < regM) THEN
					reg(0)	:= '0';
				ELSE
					reg(0)	:= '1';
					reg(2*N-1 DOWNTO N)	:= reg(2*N-1 DOWNTO N) - regM;
				END IF;
				Count := Count -1;
			ELSE		--Count = 0 ,输出
				qout(N-1 DOWNTO 0)		<= reg(N-1 DOWNTO 0);	--商
				qout(2*N-1 DOWNTO N)	<= reg(2*N-1 DOWNTO N);	--余数
				done <= '1';
			END IF;
		END IF;
	END PROCESS;
END Behavior;