📄 alu.map.rpt
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; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; |alu ; 122 (20) ; 59 ; 0 ; 23 ; 63 (10) ; 25 (1) ; 34 (9) ; 12 (0) ; |alu ;
; |booth_mul:mul| ; 48 (40) ; 25 ; 0 ; 0 ; 23 (15) ; 12 (12) ; 13 (13) ; 8 (0) ; |alu|booth_mul:mul ;
; |lpm_add_sub:add_rtl_1| ; 4 (0) ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 4 (0) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_1 ;
; |addcore:adder| ; 4 (1) ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 0 (0) ; 4 (1) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 3 (3) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:add_rtl_2| ; 4 (0) ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 4 (0) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_2 ;
; |addcore:adder| ; 4 (1) ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 0 (0) ; 4 (1) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder ;
; |a_csnbuffer:result_node| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 3 (3) ; |alu|booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node ;
; |fast_add:add| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |alu|fast_add:add ;
; |fast_div:div| ; 42 (38) ; 24 ; 0 ; 0 ; 18 (14) ; 12 (12) ; 12 (12) ; 4 (0) ; |alu|fast_div:div ;
; |lpm_add_sub:add_rtl_0| ; 4 (0) ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 4 (0) ; |alu|fast_div:div|lpm_add_sub:add_rtl_0 ;
; |addcore:adder| ; 4 (1) ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 0 (0) ; 4 (1) ; |alu|fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder ;
; |a_csnbuffer:result_node| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 3 (3) ; |alu|fast_div:div|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node ;
; |fast_sub:sub| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |alu|fast_sub:sub ;
; |fast_add:add| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |alu|fast_sub:sub|fast_add:add ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in e:/10_vhdl/alu/alu/alu.map.eqn.
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; booth_mul.vhd ; yes ;
; fast_div.vhd ; yes ;
; fast_add.vhd ; yes ;
; alu.vhd ; yes ;
; fast_Sub.vhd ; yes ;
; d:/tools/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf ; yes ;
; d:/tools/altera/quartus41/libraries/megafunctions/addcore.inc ; yes ;
; d:/tools/altera/quartus41/libraries/megafunctions/addcore.tdf ; yes ;
; d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf ; yes ;
; d:/tools/altera/quartus41/libraries/megafunctions/altshift.tdf ; yes ;
+-------------------------------------------------------------------+-----------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 122 ;
; Total combinational functions ; 97 ;
; Total 4-input functions ; 43 ;
; Total 3-input functions ; 39 ;
; Total 2-input functions ; 15 ;
; Total 1-input functions ; 0 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 59 ;
; Total logic cells in carry chains ; 12 ;
; I/O pins ; 23 ;
; Maximum fan-out node ; Clk ;
; Maximum fan-out ; 59 ;
; Total fan-out ; 449 ;
; Average fan-out ; 3.10 ;
+-----------------------------------+---------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 0 ;
; Number of synthesis-generated cells ; 122 ;
; Number of WYSIWYG LUTs ; 0 ;
; Number of synthesis-generated LUTs ; 97 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 59 ;
; Number of cells with combinational logic only ; 63 ;
; Number of cells with registers only ; 25 ;
; Number of cells with combinational logic and registers ; 34 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 25 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sat Dec 24 23:25:00 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off alu -c alu
Info: Found 2 design units, including 1 entities, in source file booth_mul.vhd
Info: Found design unit 1: booth_mul-Behavior
Info: Found entity 1: booth_mul
Info: Found 2 design units, including 1 entities, in source file fast_div.vhd
Info: Found design unit 1: fast_div-Behavior
Info: Found entity 1: fast_div
Info: Found 2 design units, including 1 entities, in source file fast_add.vhd
Info: Found design unit 1: fast_add-Behavior
Info: Found entity 1: fast_add
Info: Found 2 design units, including 1 entities, in source file alu.vhd
Info: Found design unit 1: alu-Behavior
Info: Found entity 1: alu
Info: Found 2 design units, including 1 entities, in source file fast_Sub.vhd
Info: Found design unit 1: fast_sub-Behavior
Info: Found entity 1: fast_sub
Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus41/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus41/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Implemented 145 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 10 output pins
Info: Implemented 122 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Dec 24 23:25:03 2005
Info: Elapsed time: 00:00:02
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