alu.hier_info

实现4位加减乘除的alu

|alu
A[0] => fast_div:div.divdend[0]
A[0] => booth_mul:mul.A[0]
A[0] => fast_sub:sub.A[0]
A[0] => fast_add:add.A[0]
A[1] => fast_div:div.divdend[1]
A[1] => booth_mul:mul.A[1]
A[1] => fast_sub:sub.A[1]
A[1] => fast_add:add.A[1]
A[2] => fast_div:div.divdend[2]
A[2] => booth_mul:mul.A[2]
A[2] => fast_sub:sub.A[2]
A[2] => fast_add:add.A[2]
A[3] => fast_div:div.divdend[3]
A[3] => booth_mul:mul.A[3]
A[3] => fast_sub:sub.A[3]
A[3] => fast_add:add.A[3]
B[0] => fast_div:div.divisor[0]
B[0] => booth_mul:mul.B[0]
B[0] => fast_sub:sub.B[0]
B[0] => fast_add:add.B[0]
B[1] => fast_div:div.divisor[1]
B[1] => booth_mul:mul.B[1]
B[1] => fast_sub:sub.B[1]
B[1] => fast_add:add.B[1]
B[2] => fast_div:div.divisor[2]
B[2] => booth_mul:mul.B[2]
B[2] => fast_sub:sub.B[2]
B[2] => fast_add:add.B[2]
B[3] => fast_div:div.divisor[3]
B[3] => booth_mul:mul.B[3]
B[3] => fast_sub:sub.B[3]
B[3] => fast_add:add.B[3]
Ci => fast_sub:sub.bin
Ci => fast_add:add.Cin
Clk => qout[6]~reg0.CLK
Clk => qout[5]~reg0.CLK
Clk => qout[4]~reg0.CLK
Clk => qout[3]~reg0.CLK
Clk => qout[2]~reg0.CLK
Clk => qout[1]~reg0.CLK
Clk => qout[0]~reg0.CLK
Clk => Co~reg0.CLK
Clk => done~reg0.CLK
Clk => fast_div:div.Clk
Clk => booth_mul:mul.Clk
Clk => qout[7]~reg0.CLK
load => fast_div:div.load
load => booth_mul:mul.load
optional[0] => Mux~0.IN3
optional[0] => Mux~1.IN3
optional[0] => Mux~2.IN3
optional[0] => Mux~3.IN3
optional[0] => Mux~4.IN1
optional[0] => Mux~5.IN1
optional[0] => Mux~6.IN1
optional[0] => Mux~7.IN1
optional[0] => Mux~8.IN1
optional[0] => Mux~9.IN3
optional[1] => Mux~0.IN2
optional[1] => Mux~1.IN2
optional[1] => Mux~2.IN2
optional[1] => Mux~3.IN2
optional[1] => Mux~4.IN0
optional[1] => Mux~5.IN0
optional[1] => Mux~6.IN0
optional[1] => Mux~7.IN0
optional[1] => Mux~8.IN0
optional[1] => Mux~9.IN2
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Co <= Co~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE


|alu|fast_add:add
A[0] => Sum_Buf~0.IN0
A[0] => Carry~0.IN0
A[0] => Carry~1.IN0
A[1] => Sum_Buf~2.IN0
A[1] => Carry~4.IN0
A[1] => Carry~5.IN0
A[2] => Sum_Buf~4.IN0
A[2] => Carry~8.IN0
A[2] => Carry~9.IN0
A[3] => Sum_Buf~6.IN0
A[3] => Carry~12.IN0
A[3] => Carry~13.IN0
B[0] => Sum_Buf~0.IN1
B[0] => Carry~0.IN1
B[0] => Carry~1.IN1
B[1] => Sum_Buf~2.IN1
B[1] => Carry~4.IN1
B[1] => Carry~5.IN1
B[2] => Sum_Buf~4.IN1
B[2] => Carry~8.IN1
B[2] => Carry~9.IN1
B[3] => Sum_Buf~6.IN1
B[3] => Carry~12.IN1
B[3] => Carry~13.IN1
Cin => Sum_Buf~1.IN0
Cin => Carry~2.IN0
Sum[0] <= Sum_Buf~1.DB_MAX_OUTPUT_PORT_TYPE
Sum[1] <= Sum_Buf~3.DB_MAX_OUTPUT_PORT_TYPE
Sum[2] <= Sum_Buf~5.DB_MAX_OUTPUT_PORT_TYPE
Sum[3] <= Sum_Buf~7.DB_MAX_OUTPUT_PORT_TYPE
Cout <= Carry~15.DB_MAX_OUTPUT_PORT_TYPE


|alu|fast_sub:sub
A[0] => fast_add:add.A[0]
A[1] => fast_add:add.A[1]
A[2] => fast_add:add.A[2]
A[3] => fast_add:add.A[3]
B[0] => fast_add:add.B[0]
B[1] => fast_add:add.B[1]
B[2] => fast_add:add.B[2]
B[3] => fast_add:add.B[3]
bin => fast_add:add.Cin
Diff[0] <= fast_add:add.Sum[0]
Diff[1] <= fast_add:add.Sum[1]
Diff[2] <= fast_add:add.Sum[2]
Diff[3] <= fast_add:add.Sum[3]
bout <= fast_add:add.Cout


|alu|fast_sub:sub|fast_add:add
A[0] => Sum_Buf~0.IN0
A[0] => Carry~0.IN0
A[0] => Carry~1.IN0
A[1] => Sum_Buf~2.IN0
A[1] => Carry~4.IN0
A[1] => Carry~5.IN0
A[2] => Sum_Buf~4.IN0
A[2] => Carry~8.IN0
A[2] => Carry~9.IN0
A[3] => Sum_Buf~6.IN0
A[3] => Carry~12.IN0
A[3] => Carry~13.IN0
B[0] => Sum_Buf~0.IN1
B[0] => Carry~0.IN1
B[0] => Carry~1.IN1
B[1] => Sum_Buf~2.IN1
B[1] => Carry~4.IN1
B[1] => Carry~5.IN1
B[2] => Sum_Buf~4.IN1
B[2] => Carry~8.IN1
B[2] => Carry~9.IN1
B[3] => Sum_Buf~6.IN1
B[3] => Carry~12.IN1
B[3] => Carry~13.IN1
Cin => Sum_Buf~1.IN0
Cin => Carry~2.IN0
Sum[0] <= Sum_Buf~1.DB_MAX_OUTPUT_PORT_TYPE
Sum[1] <= Sum_Buf~3.DB_MAX_OUTPUT_PORT_TYPE
Sum[2] <= Sum_Buf~5.DB_MAX_OUTPUT_PORT_TYPE
Sum[3] <= Sum_Buf~7.DB_MAX_OUTPUT_PORT_TYPE
Cout <= Carry~15.DB_MAX_OUTPUT_PORT_TYPE


|alu|booth_mul:mul
A[0] => regM[0].DATAIN
A[1] => regM[1].DATAIN
A[2] => regM[2].DATAIN
A[3] => regM[3].DATAIN
B[0] => reg~16.DATAB
B[1] => reg~15.DATAB
B[2] => reg~14.DATAB
B[3] => reg~13.DATAB
Clk => Count[2].CLK
Clk => Count[1].CLK
Clk => Count[0].CLK
Clk => reg[8].CLK
Clk => reg[7].CLK
Clk => reg[6].CLK
Clk => reg[5].CLK
Clk => reg[4].CLK
Clk => reg[3].CLK
Clk => reg[2].CLK
Clk => reg[1].CLK
Clk => reg[0].CLK
Clk => regM[3].CLK
Clk => regM[2].CLK
Clk => regM[1].CLK
Clk => regM[0].CLK
Clk => qout[7]~reg0.CLK
Clk => qout[6]~reg0.CLK
Clk => qout[5]~reg0.CLK
Clk => qout[4]~reg0.CLK
Clk => qout[3]~reg0.CLK
Clk => qout[2]~reg0.CLK
Clk => qout[1]~reg0.CLK
Clk => qout[0]~reg0.CLK
Clk => done~reg0.CLK
load => done~1.OUTPUTSELECT
load => Count~3.OUTPUTSELECT
load => Count~4.OUTPUTSELECT
load => Count~5.OUTPUTSELECT
load => reg~9.OUTPUTSELECT
load => reg~10.OUTPUTSELECT
load => reg~11.OUTPUTSELECT
load => reg~12.OUTPUTSELECT
load => reg~13.OUTPUTSELECT
load => reg~14.OUTPUTSELECT
load => reg~15.OUTPUTSELECT
load => reg~16.OUTPUTSELECT
load => reg~17.OUTPUTSELECT
load => regM[3].ENA
load => regM[2].ENA
load => regM[1].ENA
load => regM[0].ENA
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE


|alu|fast_div:div
divdend[0] => reg~17.DATAB
divdend[1] => reg~16.DATAB
divdend[2] => reg~15.DATAB
divdend[3] => reg~14.DATAB
divisor[0] => regM[0].DATAIN
divisor[1] => regM[1].DATAIN
divisor[2] => regM[2].DATAIN
divisor[3] => regM[3].DATAIN
Clk => Count[2].CLK
Clk => Count[1].CLK
Clk => Count[0].CLK
Clk => regM[3].CLK
Clk => regM[2].CLK
Clk => regM[1].CLK
Clk => regM[0].CLK
Clk => reg[7].CLK
Clk => reg[6].CLK
Clk => reg[5].CLK
Clk => reg[4].CLK
Clk => reg[3].CLK
Clk => reg[2].CLK
Clk => reg[1].CLK
Clk => reg[0].CLK
Clk => qout[7]~reg0.CLK
Clk => qout[6]~reg0.CLK
Clk => qout[5]~reg0.CLK
Clk => qout[4]~reg0.CLK
Clk => qout[3]~reg0.CLK
Clk => qout[2]~reg0.CLK
Clk => qout[1]~reg0.CLK
Clk => qout[0]~reg0.CLK
Clk => done~reg0.CLK
load => done~1.OUTPUTSELECT
load => Count~3.OUTPUTSELECT
load => Count~4.OUTPUTSELECT
load => Count~5.OUTPUTSELECT
load => reg~11.OUTPUTSELECT
load => reg~12.OUTPUTSELECT
load => reg~13.OUTPUTSELECT
load => reg~14.OUTPUTSELECT
load => reg~15.OUTPUTSELECT
load => reg~16.OUTPUTSELECT
load => reg~17.OUTPUTSELECT
load => regM[3].ENA
load => regM[2].ENA
load => regM[1].ENA
load => regM[0].ENA
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE