alu.tan.qmsg

实现4位加减乘除的alu

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "Clk qout\[7\] qout\[7\]~reg0 9.900 ns register " "Info: Minimum tco from clock Clk to destination pin qout\[7\] through register qout\[7\]~reg0 is 9.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock Clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns qout\[7\]~reg0 2 REG LC8_B22 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B22; Fanout = 1; REG Node = 'qout\[7\]~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk qout[7]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk qout[7]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qout\[7\]~reg0 1 REG LC8_B22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 1; REG Node = 'qout\[7\]~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { qout[7]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 5.100 ns qout\[7\] 2 PIN PIN_65 0 " "Info: 2: + IC(1.200 ns) + CELL(3.900 ns) = 5.100 ns; Loc. = PIN_65; Fanout = 0; PIN Node = 'qout\[7\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "5.100 ns" { qout[7]~reg0 qout[7] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 76.47 % " "Info: Total cell delay = 3.900 ns ( 76.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 23.53 % " "Info: Total interconnect delay = 1.200 ns ( 23.53 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "5.100 ns" { qout[7]~reg0 qout[7] } "NODE_NAME" } } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk qout[7]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "5.100 ns" { qout[7]~reg0 qout[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 24 23:25:11 2005 " "Info: Processing ended: Sat Dec 24 23:25:11 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}