alu.tan.qmsg

实现4位加减乘除的alu

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node Clk is an undefined clock" {  } { { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } } { "d:/tools/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/tools/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register booth_mul:mul\|reg\[6\] register booth_mul:mul\|reg\[6\] 68.97 MHz 14.5 ns Internal " "Info: Clock Clk has Internal fmax of 68.97 MHz between source register booth_mul:mul\|reg\[6\] and destination register booth_mul:mul\|reg\[6\] (period= 14.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.300 ns + Longest register register " "Info: + Longest register to register delay is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns booth_mul:mul\|reg\[6\] 1 REG LC1_B14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B14; Fanout = 7; REG Node = 'booth_mul:mul\|reg\[6\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.900 ns) 2.800 ns booth_mul:mul\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 2 COMB LC6_B15 2 " "Info: 2: + IC(1.900 ns) + CELL(0.900 ns) = 2.800 ns; Loc. = LC6_B15; Fanout = 2; COMB Node = 'booth_mul:mul\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.800 ns" { booth_mul:mul|reg[6] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 3.900 ns booth_mul:mul\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 3 COMB LC7_B15 1 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 3.900 ns; Loc. = LC7_B15; Fanout = 1; COMB Node = 'booth_mul:mul\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "1.100 ns" { booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } } } { "d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/tools/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 7.600 ns booth_mul:mul\|reg~2862 4 COMB LC8_B13 1 " "Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 7.600 ns; Loc. = LC8_B13; Fanout = 1; COMB Node = 'booth_mul:mul\|reg~2862'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.700 ns" { booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] booth_mul:mul|reg~2862 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 9.600 ns booth_mul:mul\|reg~2863 5 COMB LC1_B13 1 " "Info: 5: + IC(0.600 ns) + CELL(1.400 ns) = 9.600 ns; Loc. = LC1_B13; Fanout = 1; COMB Node = 'booth_mul:mul\|reg~2863'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { booth_mul:mul|reg~2862 booth_mul:mul|reg~2863 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 12.300 ns booth_mul:mul\|reg\[6\] 6 REG LC1_B14 7 " "Info: 6: + IC(1.800 ns) + CELL(0.900 ns) = 12.300 ns; Loc. = LC1_B14; Fanout = 7; REG Node = 'booth_mul:mul\|reg\[6\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.700 ns" { booth_mul:mul|reg~2863 booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns 50.41 % " "Info: Total cell delay = 6.200 ns ( 50.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 49.59 % " "Info: Total interconnect delay = 6.100 ns ( 49.59 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "12.300 ns" { booth_mul:mul|reg[6] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] booth_mul:mul|reg~2862 booth_mul:mul|reg~2863 booth_mul:mul|reg[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock Clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns booth_mul:mul\|reg\[6\] 2 REG LC1_B14 7 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B14; Fanout = 7; REG Node = 'booth_mul:mul\|reg\[6\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock Clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns booth_mul:mul\|reg\[6\] 2 REG LC1_B14 7 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B14; Fanout = 7; REG Node = 'booth_mul:mul\|reg\[6\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "12.300 ns" { booth_mul:mul|reg[6] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] booth_mul:mul|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] booth_mul:mul|reg~2862 booth_mul:mul|reg~2863 booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|reg[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "qout\[3\]~reg0 A\[0\] Clk 22.600 ns register " "Info: tsu for register qout\[3\]~reg0 (data pin = A\[0\], clock pin = Clk) is 22.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.200 ns + Longest pin register " "Info: + Longest pin to register delay is 25.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns A\[0\] 1 PIN PIN_47 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_47; Fanout = 5; PIN Node = 'A\[0\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { A[0] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.900 ns) 8.200 ns fast_add:add\|Carry~343 2 COMB LC2_C21 2 " "Info: 2: + IC(3.200 ns) + CELL(1.900 ns) = 8.200 ns; Loc. = LC2_C21; Fanout = 2; COMB Node = 'fast_add:add\|Carry~343'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "5.100 ns" { A[0] fast_add:add|Carry~343 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.900 ns) 12.500 ns fast_add:add\|Carry~344 3 COMB LC2_C13 2 " "Info: 3: + IC(2.400 ns) + CELL(1.900 ns) = 12.500 ns; Loc. = LC2_C13; Fanout = 2; COMB Node = 'fast_add:add\|Carry~344'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "4.300 ns" { fast_add:add|Carry~343 fast_add:add|Carry~344 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 15.000 ns fast_add:add\|Carry~345 4 COMB LC5_C13 2 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 15.000 ns; Loc. = LC5_C13; Fanout = 2; COMB Node = 'fast_add:add\|Carry~345'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.500 ns" { fast_add:add|Carry~344 fast_add:add|Carry~345 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.900 ns) 19.400 ns fast_add:add\|Sum\[3\] 5 COMB LC1_C11 1 " "Info: 5: + IC(2.500 ns) + CELL(1.900 ns) = 19.400 ns; Loc. = LC1_C11; Fanout = 1; COMB Node = 'fast_add:add\|Sum\[3\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "4.400 ns" { fast_add:add|Carry~345 fast_add:add|Sum[3] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/fast_add.vhd" "" "" { Text "e:/10_vhdl/alu/alu/fast_add.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 23.200 ns Mux~36 6 COMB LC5_C4 1 " "Info: 6: + IC(1.900 ns) + CELL(1.900 ns) = 23.200 ns; Loc. = LC5_C4; Fanout = 1; COMB Node = 'Mux~36'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.800 ns" { fast_add:add|Sum[3] Mux~36 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 25.200 ns qout\[3\]~reg0 7 REG LC1_C4 1 " "Info: 7: + IC(0.600 ns) + CELL(1.400 ns) = 25.200 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 'qout\[3\]~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Mux~36 qout[3]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 55.56 % " "Info: Total cell delay = 14.000 ns ( 55.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.200 ns 44.44 % " "Info: Total interconnect delay = 11.200 ns ( 44.44 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "25.200 ns" { A[0] fast_add:add|Carry~343 fast_add:add|Carry~344 fast_add:add|Carry~345 fast_add:add|Sum[3] Mux~36 qout[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock Clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns qout\[3\]~reg0 2 REG LC1_C4 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 'qout\[3\]~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk qout[3]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk qout[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "25.200 ns" { A[0] fast_add:add|Carry~343 fast_add:add|Carry~344 fast_add:add|Carry~345 fast_add:add|Sum[3] Mux~36 qout[3]~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk qout[3]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Co Co~reg0 11.100 ns register " "Info: tco from clock Clk to destination pin Co through register Co~reg0 is 11.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 3.900 ns + Longest register " "Info: + Longest clock path from clock Clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns Co~reg0 2 REG LC4_C2 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C2; Fanout = 2; REG Node = 'Co~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk Co~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk Co~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Longest register pin " "Info: + Longest register to pin delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Co~reg0 1 REG LC4_C2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C2; Fanout = 2; REG Node = 'Co~reg0'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Co~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(3.900 ns) 6.300 ns Co 2 PIN PIN_60 0 " "Info: 2: + IC(2.400 ns) + CELL(3.900 ns) = 6.300 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Co'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "6.300 ns" { Co~reg0 Co } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 61.90 % " "Info: Total cell delay = 3.900 ns ( 61.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 38.10 % " "Info: Total interconnect delay = 2.400 ns ( 38.10 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "6.300 ns" { Co~reg0 Co } "NODE_NAME" } } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk Co~reg0 } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "6.300 ns" { Co~reg0 Co } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "booth_mul:mul\|regM\[3\] A\[3\] Clk 0.900 ns register " "Info: th for register booth_mul:mul\|regM\[3\] (data pin = A\[3\], clock pin = Clk) is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock Clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns Clk 1 CLK PIN_43 59 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'Clk'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns booth_mul:mul\|regM\[3\] 2 REG LC2_B19 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 2; REG Node = 'booth_mul:mul\|regM\[3\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.000 ns" { Clk booth_mul:mul|regM[3] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|regM[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns A\[3\] 1 PIN PIN_42 7 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 7; PIN Node = 'A\[3\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "" { A[3] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/alu.vhd" "" "" { Text "e:/10_vhdl/alu/alu/alu.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.900 ns) 4.400 ns booth_mul:mul\|regM\[3\] 2 REG LC2_B19 2 " "Info: 2: + IC(1.600 ns) + CELL(0.900 ns) = 4.400 ns; Loc. = LC2_B19; Fanout = 2; REG Node = 'booth_mul:mul\|regM\[3\]'" {  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "2.500 ns" { A[3] booth_mul:mul|regM[3] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/booth_mul.vhd" "" "" { Text "e:/10_vhdl/alu/alu/booth_mul.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 63.64 % " "Info: Total cell delay = 2.800 ns ( 63.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 36.36 % " "Info: Total interconnect delay = 1.600 ns ( 36.36 % )" {  } {  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "4.400 ns" { A[3] booth_mul:mul|regM[3] } "NODE_NAME" } } }  } 0}  } { { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "3.900 ns" { Clk booth_mul:mul|regM[3] } "NODE_NAME" } } } { "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" "" "" { Report "e:/10_vhdl/alu/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "e:/10_vhdl/alu/alu/db/alu.quartus_db" { Floorplan "" "" "4.400 ns" { A[3] booth_mul:mul|regM[3] } "NODE_NAME" } } }  } 0}