booth_mul.vhd

来自「实现4位加减乘除的alu」· VHDL 代码 · 共 48 行

--布斯乘法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY booth_mul IS
	GENERIC(N:	integer	:=	4);
    PORT(A		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Clk	:IN		STD_LOGIC;
		 load	:IN		STD_LOGIC;
         qout	:OUT	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);
         done	:OUT	STD_LOGIC);
END booth_mul;

ARCHITECTURE Behavior OF booth_mul IS
BEGIN
	PROCESS(Clk)
	VARIABLE reg	:	STD_LOGIC_VECTOR(2*N DOWNTO 0);
	VARIABLE regM	:	STD_LOGIC_vECTOR(N-1 DOWNTO 0);
	VARIABLE Count	:	INTEGER RANGE 0 TO N;
	BEGIN
		IF Clk'EVENT AND Clk='1' THEN
			IF load = '1' THEN		--加载并赋初值
				done <= '0';
				Count	:= N;
				reg(2*N downto N+1) := (OTHERS=>'0');
				reg(N DOWNTO 1)		:= B;
				regM				:= A;
				reg(0)				:= '0';
			ELSIF Count /= 0 THEN
				CASE reg(1 DOWNTO 0) IS
					WHEN "01" =>
						reg(2*N DOWNTO N+1)	:= reg(2*N DOWNTO N+1) + regM;	
					WHEN "10" =>
						reg(2*N DOWNTO N+1)	:= reg(2*N DOWNTO N+1) - regM;	
					WHEN OTHERS=>
						reg := reg;
				END CASE;
				reg(2*N-1 DOWNTO 0) :=	reg(2*N DOWNTO 1);	--循环右移
				Count := Count -1;
			ELSE		--Count = 0,所以输出
				qout <= reg(2*N DOWNTO 1);
				done <= '1';
			END IF;
		END IF;
	END PROCESS;
END Behavior;