fast_add.vhd

来自「实现4位加减乘除的alu」· VHDL 代码 · 共 28 行

--快速加法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY fast_add IS
	GENERIC(N:	integer	:=	4);
    PORT(A		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cin	:IN		STD_LOGIC;
         Sum	:OUT	STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cout	:OUT	STD_LOGIC);
END fast_add;

ARCHITECTURE Behavior OF fast_add IS
BEGIN
	PROCESS(A,B,Cin)
	VARIABLE Carry		:STD_LOGIC;
	VARIABLE Sum_Buf	:STD_LOGIC_VECTOR(N-1 DOWNTO 0);
	BEGIN
		Carry	:=	Cin;
		FOR i IN 0 TO N-1 LOOP
			Sum_Buf(i) 	:= ( A(i) XOR B(i) ) XOR Carry;
			Carry  		:= ( A(i) AND B(i) ) OR ( (A(i) OR B(i)) AND Carry );
		END	LOOP;
		Sum		<=Sum_Buf;
		Cout	<= Carry;
	END PROCESS;
END Behavior;